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==Serial SLC NAND Memory==
Product family 25N.

===[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]===
A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bytes are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).

The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.

The device has JEDEC Manufacturer ID 0xEF and Device ID 0xAA21.

Bad blocks are marked at the factory with a non-0xff byte as their first byte, and a non-0xff byte as the first byte of the first page's Spare Area (i.e. all blocks marked with 0xff as their first byte, and as the first byte of the first page's Spare Area, are considered good). Before executing the first program or erase instruction, pages ought be inspected, and added to the LUT if necessary.

====Packages====
* 8-pad WSON 8x6mm (package code ZE)
* 16-pin SOIC 300-mil (package code SF)
* 1x4 + 4x5 24-ball 8x6mm TFBGA (package code TB)
* 4x6 24-ball 8x6mm TFBGA (package code TC)

====Lines====
* CLK serial clock input
* /CS chip select input
** High deselects the device, putting it into standby mode (reduced power consumption)
** Transition to low places device into active mode
** /CS must track VCC during initialization and shutdown
* DI (IO0) data input / I/O-0
** SPI must use this for writing. Dual- and Quad-SPI use it bidirectionally.
* DO (IO1) data output / I/O-1
** SPI must use this for reading. Dual- and Quad-SPI use it bidirectionally.
* /WP (IO2) write protect input / I/O-2
** Used only in Hardware Protection mode (incompatible with Quad-SPI)
* /HOLD (IO3) hold input / I/O-3
** Used only in Hardware Protection mode (incompatible with Quad-SPI)
* VCC power (2.7V--3.6V)
* GND
Data is written on the rising edge of CLK, and read on the falling edge.

====Status Registers====
Used with the ReadStatusRegister and WriteStatusRegister commands. Factory defaults are 1 for the 4 BP bits, TB, and ECC-E, and 0 for all other bits (though this can be changed via OTP locking).
* Protection Register (SR1)
** MSB: Status register protect 0
** B6, B5, B4, B3: Block protection bits, all initialized to 1 (unless set via OTP)
** B2: TP (Type of protection). When 1, protection applies to the lower end of the protected blocks; when 0, the upper end
*** When BP3 and either BP2 or BP1 are 1, TP is a don't care -- everything is protected
*** When all BP bits are 0, TP is a don't care -- nothing is protected
** B1: Write protection mode. Defaults to 0 (Software protection, Quad-SPI)
*** Hardware write protection (/WP, /HOLD) cannot be used with Quad-SPI
** LSB: Status register protect 1
* Configuration Register (SR2)
** MSB: OTP lock. Once set to 1, the OTP area (10 2KB pages) cannot be reprogrammed.
** B6: OTP access enable. Must be set to 1 to access OTP area.
** B5: SR1 lock. Once set to 1, selected SR1 values are OTP-locked.
** B4: ECC enable. Defaults to 1. Controls on-device bidirectional ECC.
** B3: BUF mode select. Default depends on part number (IG defaults to 1). 1 is buffer read mode, 0 is continuous.
*** Buffer mode: provided a starting byte and a page, returns the page starting at that byte, plus the Spare Area
*** Continuous mode: provided a page, returns (multiple pages of) memory starting at the first byte of that page
*** Only buffer mode allows the Spare Area to be read
** B2, B1, LSB: reserved
* Status Register (SR3)
** MSB: reserved
** B6: LUT full, set to 1 when all 20 entries of the LUT are used
** B5: ECC-1 (ECC status), set to 0 on successful read (even with corrections), 1 on uncorrected error
** B4: ECC-0 (ECC details)
*** If ECC-1 is 0, 0 indicates no corrections, 1 indicates corrections.
*** If ECC-1 is 1, 0 indicates unusable page, 1 indicates multiple unusable pages (during continuous read)
*** Both ECC bits are reset to 0 only on initialization and following RESET
** B3: PFAIL (Program failure), set to 1 when a ProgramExecute command fails
** B2: EFAIL (Erase failure), set to 1 when a BlockErase command fails
*** Both PFAIL and EFAIL are reset at the beginning of each ProgramExecute or BlockErase
** B1: Write-enabled latch, set to 1 following WriteEnable instruction, set to 0 following many instructions
** B0: Busy, set to 1 while instructions are not being accepted following many instructions

====Instructions====
27 instructions are supported, generally compatible with the SpiFlash NOR command set. Instruction read is initiated on the falling edge of /CS, and completion indicated by the rising edge. Write, Program, and Erase instructions must drive CS high on a byte boundary (8*n CLK cycles following /CS falling); this is relevant when using Dual- or Quad-SPI (where a byte requires 4 or 2 rather than 8 clocks). Most instructions are ignored when the BUSY bit of SR3 is set.
* 0xFF -- RESET. Data corruption can result if RESET is issued while BUSY is high.
* 0x9F -- ReadJEDEC, returns 0xEFAA21
* 0x0F (also 0x05) -- ReadStatusRegister, 1-byte argument identifying SR, 1-byte return, can be used while BUSY
* 0x1F (also 0x01) -- WriteStatusRegister, 1-byte argument identifying SR, 1-byte value
* 0x06 -- WriteEnable. Must be issued prior to PageProgram, QuadPageProgram, BlockErase, and BadBlockManagement
* 0x04 -- WriteDisable. Manually sets WEL. Set 0 following RESET or any instruction mentioned in WriteEnable
* 0xA1 -- BadBlockManagement. Add a logical -> physical page mapping to the LUT, if possible
* 0xA5 -- ReadBBM. Returns the 20 32-bit BBM entries, type-tagged by the 2 MSB of the logical page address
* 0xA9 -- LastECCFailure. Returns the last page to see an uncorrectable failure (ECC-0 is 1)
* 0xD8 -- BlockErase. 8 dummy clocks followed by 2-byte block address. Writes all 1s to the specified 128KB block
* 0x02 -- LoadProgramData. Fill the 2,112B data buffer. 2-byte column address argument, followed by data bytes. Unprovided bytes are 0xff
* 0x84 -- RandomLoadProgramData. LoadProgramData, but don't bother resetting unused bytes in the data buffer
* 0x32 -- QuadLoadProgramData. LoadProgramData using 4 pins for data transfer
* 0x34 -- QuadRandomLoadProgramData. RandomLoadProgramData using 4 pins for data transfer
* 0x10 -- ProgramExecute. 8 dummy clocks followed by 2-byte page address. The data buffer is written to the page.
** Pages must be written sequentially within a block!
* 0x13 -- PageDataRead. 8 dummy clocks followed by 2-byte page address. The data buffer is filled from the page.
** If OTP is enabled, page addresses 0x0--0xb are remapped to the Unique ID Page, Parameter Page, and 10 OTP pages
* 0x03 -- ReadData. Dependent on BUF mode and OTP-E bit:
** Buffer mode OR OTP enabled: 8 dummy clocks followed by 2-byte column address. The data buffer is spooled from the address to the end
** Continuous mode: 24 dummy clocks. The first 2KB of the data buffer are spooled (i.e. not the Spare Area)
** Continuous mode will continue through subsequent pages
* 0x6b -- QuadFastRead. ReadData, using 4 pins for data transfer
* 0xeb -- QuadFastReadAddr. QuadFastRead, using 4 pins for address transfer