CPUID - revision history

Dank: link to EFLAGS

2011-08-04T03:49:36Z

link to EFLAGS

← Older revision		Revision as of 03:49, 4 August 2011
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	The 8086/88 is distinguished from the 80286 by attempting to clear bits 12 - 15 of the FLAGs register, The 8086/88 will always set these bits, regardless of what values are popped into them (see Listing One). The 286 treats these bits differently. In real mode, these bits are always cleared by the 286; in protected mode, they are used for IOPL (I/O Privilege Level) and NT (Nested Task). To continue the detection code, you need to set bits 12 - 15 in the FLAGs register, and see if they are cleared by the processor. If they are, then a 286 has been detected (see Listing Two).		The 8086/88 is distinguished from the 80286 by attempting to clear bits 12 - 15 of the FLAGs register, The 8086/88 will always set these bits, regardless of what values are popped into them (see Listing One). The 286 treats these bits differently. In real mode, these bits are always cleared by the 286; in protected mode, they are used for IOPL (I/O Privilege Level) and NT (Nested Task). To continue the detection code, you need to set bits 12 - 15 in the FLAGs register, and see if they are cleared by the processor. If they are, then a 286 has been detected (see Listing Two).

	If you ~~gethis~~ point in the algorithm, you know you have at least a 386. Therefore, it is safe to use 32-bit instructions, like PUSHFD. This will be necessary in detecting the difference between a 386 and 486. These processors are distinguished from each othmpting to set the AC flag in the ~~EFLAGs~~ register. This flag was introduced in the 486, The 386 never sets this bit, and always clhen it is set by POPFD. Therefore, to detect the difference between these processor generations, the algorithm attempts to set thiee if it is latched or cleared by the processor (see Listing Three).		If you get to this point in the algorithm, you know you have at least a 386. Therefore, it is safe to use 32-bit instructions, like PUSHFD. This will be necessary in detecting the difference between a 386 and 486. These processors are distinguished from each othmpting to set the AC flag in the [[EFLAGS]] register. This flag was introduced in the 486, The 386 never sets this bit, and always clhen it is set by POPFD. Therefore, to detect the difference between these processor generations, the algorithm attempts to set thiee if it is latched or cleared by the processor (see Listing Three).

	At this point in the algorithm, you're almost home. To detect the difference between the 486 and the Pentium, you attempt to set another new ~~EFLAG~~ bit (bit-21) called the "ID flag." This flag has only one purpose - to indicate the presence of the CPUID instruction. This bit was first introduced on the Pentium, but later retrofitted into the 486. If the CPUID instruction exists on either processor, it may be executed to return the processor-identification information. 486s without the CPUID instruction will not be able to toggle this bit. Therefore, it is safe to execute a sequence of instructions on either processor that detects the processor's ability to toggle this bit ~~(see Listing Four)~~.		At this point in the algorithm, you're almost home. To detect the difference between the 486 and the Pentium, you attempt to set another new [[EFLAGS]] bit (bit-21) called the "ID flag." This flag has only one purpose - to indicate the presence of the CPUID instruction. This bit was first introduced on the Pentium, but later retrofitted into the 486. If the CPUID instruction exists on either processor, it may be executed to return the processor-identification information. 486s without the CPUID instruction will not be able to toggle this bit. Therefore, it is safe to execute a sequence of instructions on either processor that detects the processor's ability to toggle this bit.

	Once the algorithm gets to this point, you can execute the CPUID instruction to obtain the processor identification. This instruction can be run in any processor mode, at any privilege level. On the Pentium and 486, the CPUID instruction has two levels:		Once the algorithm gets to this point, you can execute the CPUID instruction to obtain the processor identification. This instruction can be run in any processor mode, at any privilege level. On the Pentium and 486, the CPUID instruction has two levels:
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	The complete Intel algorithm is available in AP-485, or via anonymous FTP at ftp://ftp.intel.com/pub/IAL/tools_utils_demos/cpuid3.zip.		The complete Intel algorithm is available in AP-485, or via anonymous FTP at ftp://ftp.intel.com/pub/IAL/tools_utils_demos/cpuid3.zip.

	==See Also==		==See Also==
	* [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction" (2009-08)		* [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction" (2009-08)

Dank: moved Cpuid to CPUID: more accurate

2011-01-12T10:02:36Z

moved Cpuid to CPUID: more accurate

← Older revision		Revision as of 10:02, 12 January 2011
(No difference)

Dank: /* Using libtorque for system discovery */

2009-11-07T15:05:42Z

Using libtorque for system discovery

← Older revision		Revision as of 15:05, 7 November 2009
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	==Using [[libtorque]] for system discovery==		==Using [[libtorque]] for system discovery==
	A very complete, open source CPUID implementation is available in [[libtorque]]~~. See~~ [http://github.com/dankamongmen/libtorque/blob/master/src/libtorque/hardware/x86cpuid.c src/libtorque/hardware/x86cpuid.c]. It's up-to-date as of 2009-11 for both Intel and AMD processors, doesn't require root privileges, supports all major affinity API's, handles SMT, multicore, and multiple physical packages, [[NUMA]] and discovers all caches and TLBs. Furthermore, it performs dynamic topology enumeration.		A very complete, open source CPUID implementation is available in [[libtorque]] (see [http://github.com/dankamongmen/libtorque/blob/master/src/libtorque/hardware/x86cpuid.c src/libtorque/hardware/x86cpuid.c]). It's up-to-date as of 2009-11 for both Intel and AMD processors, doesn't require root privileges, supports all major affinity API's, handles SMT, multicore, and multiple physical packages, [[NUMA]] and discovers all caches and TLBs. Furthermore, it performs dynamic topology enumeration.

	==CPUID and [[SMP on x86\|multiple processors]]==		==CPUID and [[SMP on x86\|multiple processors]]==

Dank at 15:05, 7 November 2009

2009-11-07T15:05:25Z

← Older revision		Revision as of 15:05, 7 November 2009
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	Loading the cpuid module creates the nodes <tt>/dev/cpu/*/cpuid</tt>. Good commands for breaking down cpuid data include <tt>cpuid</tt> and Dave Jones's <tt>x86info</tt>. A "cpuid_level" field can be found in <tt>/proc/cpuinfo</tt> (checked as of 2.6.25-rc3) for each processor in the system. There's Intel and AMD documents about using cpuid effectively, although they're given short shrift at [http://www.rcollins.org/ddj/Sep96/Sep96.html this page].		Loading the cpuid module creates the nodes <tt>/dev/cpu/*/cpuid</tt>. Good commands for breaking down cpuid data include <tt>cpuid</tt> and Dave Jones's <tt>x86info</tt>. A "cpuid_level" field can be found in <tt>/proc/cpuinfo</tt> (checked as of 2.6.25-rc3) for each processor in the system. There's Intel and AMD documents about using cpuid effectively, although they're given short shrift at [http://www.rcollins.org/ddj/Sep96/Sep96.html this page].

			==Using [[libtorque]] for system discovery==
	A very complete, open source CPUID implementation is available in [[libtorque]]. See [http://github.com/dankamongmen/libtorque/blob/master/src/libtorque/hardware/x86cpuid.c src/libtorque/hardware/x86cpuid.c]. It's up-to-date as of 2009-11 for both Intel and AMD processors, doesn't require root privileges, supports all major affinity API's, handles SMT, multicore, and multiple physical packages, [[NUMA]] and discovers all caches and TLBs. Furthermore, it performs dynamic topology enumeration.		A very complete, open source CPUID implementation is available in [[libtorque]]. See [http://github.com/dankamongmen/libtorque/blob/master/src/libtorque/hardware/x86cpuid.c src/libtorque/hardware/x86cpuid.c]. It's up-to-date as of 2009-11 for both Intel and AMD processors, doesn't require root privileges, supports all major affinity API's, handles SMT, multicore, and multiple physical packages, [[NUMA]] and discovers all caches and TLBs. Furthermore, it performs dynamic topology enumeration.

Dank at 15:04, 7 November 2009

2009-11-07T15:04:52Z

@@ Line 1: / Line 1: @@
 Loading the cpuid module creates the nodes <tt>/dev/cpu/*/cpuid</tt>. Good commands for breaking down cpuid data include <tt>cpuid</tt> and Dave Jones's <tt>x86info</tt>. A "cpuid_level" field can be found in <tt>/proc/cpuinfo</tt> (checked as of 2.6.25-rc3) for each processor in the system. There's Intel and AMD documents about using cpuid effectively, although they're given short shrift at [http://www.rcollins.org/ddj/Sep96/Sep96.html this page].
-==Availability of cpuid==
+A very complete, open source CPUID implementation is available in [[libtorque]]. See [http://github.com/dankamongmen/libtorque/blob/master/src/libtorque/hardware/x86cpuid.c src/libtorque/hardware/x86cpuid.c]. It's up-to-date as of 2009-11 for both Intel and AMD processors, doesn't require root privileges, supports all major affinity API's, handles SMT, multicore, and multiple physical packages, [[NUMA]] and discovers all caches and TLBs. Furthermore, it performs dynamic topology enumeration.
 ==CPUID and [[SMP on x86|multiple processors]]==
-Some CPUID attributes require multiple CPUID calls to retrieve (often EAX is first set to 0 to determine the highest attribute request supported, then called again with specific requests). Behavior is undefined if CPUID information from one processor is used to form requests for another (especially in a heterogeneous system). Furthermore, CPUID must be performed on each processor used -- results for one processor have no general ramifications for others (again, especially in a heterogeneous system). Thus, either:
+Some CPUID attributes require multiple CPUID calls to retrieve (often EAX is first set to 0 to determine the highest attribute request supported, then called again with specific requests). Behavior is undefined if CPUID information from one processor is used to form requests for another (especially in a heterogeneous system). Furthermore, CPUID must be performed on each processor used -- results for one processor have no general ramifications for others (again, especially in a heterogeneous system). Current AMD and Intel CPUID specifications explicitly cover only homogeneous systems. To perform system-wide detection, either
-* the process using CPUID must be bound to a single CPU by the system administrator,
+* the process must start in a [[cpuset]] containing all processors, and the process must bind itself to each CPU in turn
-* the process must be able to bind itself to a CPU (see <tt>sched_setpolicy()</tt> on [[Linux APIs|Linux]] and <tt>cpuset_setpolicy</tt> on [[FreeBSD APIs|FreeBSD]]), or
+** see <tt>sched_setpolicy()</tt> on [[Linux APIs|Linux]] and <tt>cpuset_setpolicy</tt> on [[FreeBSD APIs|FreeBSD]]), or
 * the operating system must provide a world-readable interface (ie, the process never calls CPUID directly)
 On [[Linux APIs|Linux]], the <tt>/dev/cpuid(4)</tt> device provides an obsolete interface to CPUID. On modern systems, it is chmod'd 0440, and its use is discouraged. Instead, since [http://lkml.indiana.edu/hypermail/linux/kernel/0801.3/2419.html at least 2.6.24] a [[sysfs]] interface has been supported; see <tt>/sys/devices/system/cpu/*/</tt>:<pre>[dumbledore](0) $ for i in /sys/devices/system/cpu/cpu0/cache/*/* /sys/devices/system/cpu/cpu0/topology/* ; do echo -n "`basename $i`: " && cat $i ; done
@@ Line 68: / Line 52: @@
 * Number of threads for a given level of topology can be determined via CPUID function 0x0000000B, checking ECX bits 15:8 for each level.
 ==See Also==
 * [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction" (2009-08)

Dank: /* See Also */

2009-11-03T05:27:39Z

Dank: /* CPUID and multiple threads */

2009-11-03T05:26:20Z

CPUID and multiple threads

← Older revision		Revision as of 05:26, 3 November 2009
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	[dumbledore](0) $ </pre>		[dumbledore](0) $ </pre>
	==CPUID and [[SMP on x86\|multiple threads]]==		==CPUID and [[SMP on x86\|multiple threads]]==
	* The package must support SMT. Check via bit 28 (0x1c00) of the EDX register after CPUID function 0x00000001		* The package must support SMT. Check via bit 28 (0x1c00) of the EDX register after CPUID function 0x00000001.
	* The processor must support SMT. Check via bits 23:16 of the EBX register after CPUID function 0x00000001. They must be > 1.		* The processor must support SMT. Check via bits 23:16 of the EBX register after CPUID function 0x00000001. They must be > 1.
	* Number of threads sharing a given cache can be determined via CPUID function 0x00000004, checking EAX bits 25:14 for each cache.		* Number of threads sharing a given cache can be determined via CPUID function 0x00000004, checking EAX bits 25:14 for each cache.

Dank: /* CPUID and multiple processors */

2009-11-03T05:25:45Z

CPUID and multiple processors

← Older revision		Revision as of 05:25, 3 November 2009
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	thread_siblings: 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00000101		thread_siblings: 00000000,00000000,00000000,00000000,00000000,00000000,00000000,00000101
	[dumbledore](0) $ </pre>		[dumbledore](0) $ </pre>
			==CPUID and [[SMP on x86\|multiple threads]]==
			* The package must support SMT. Check via bit 28 (0x1c00) of the EDX register after CPUID function 0x00000001
			* The processor must support SMT. Check via bits 23:16 of the EBX register after CPUID function 0x00000001. They must be > 1.
			* Number of threads sharing a given cache can be determined via CPUID function 0x00000004, checking EAX bits 25:14 for each cache.
			* Number of threads for a given level of topology can be determined via CPUID function 0x0000000B, checking ECX bits 15:8 for each level.

	==See Also==		==See Also==

Dank: /* CPUID and multiple processors */

2009-11-03T03:49:48Z

CPUID and multiple processors

← Older revision		Revision as of 03:49, 3 November 2009
Line 22:		Line 22:
	Some CPUID attributes require multiple CPUID calls to retrieve (often EAX is first set to 0 to determine the highest attribute request supported, then called again with specific requests). Behavior is undefined if CPUID information from one processor is used to form requests for another (especially in a heterogeneous system). Furthermore, CPUID must be performed on each processor used -- results for one processor have no general ramifications for others (again, especially in a heterogeneous system). Thus, either:		Some CPUID attributes require multiple CPUID calls to retrieve (often EAX is first set to 0 to determine the highest attribute request supported, then called again with specific requests). Behavior is undefined if CPUID information from one processor is used to form requests for another (especially in a heterogeneous system). Furthermore, CPUID must be performed on each processor used -- results for one processor have no general ramifications for others (again, especially in a heterogeneous system). Thus, either:
	* the process using CPUID must be bound to a single CPU by the system administrator,		* the process using CPUID must be bound to a single CPU by the system administrator,
	* the process must be able to bind itself to a CPU (~~usually requiring root~~), or		* the process must be able to bind itself to a CPU (see <tt>sched_setpolicy()</tt> on [[Linux APIs\|Linux]] and <tt>cpuset_setpolicy</tt> on [[FreeBSD APIs\|FreeBSD]]), or
	* the operating system must provide a world-readable interface (ie, the process never calls CPUID directly)		* the operating system must provide a world-readable interface (ie, the process never calls CPUID directly)
	On [[Linux APIs\|Linux]], the <tt>/dev/cpuid(4)</tt> device provides an obsolete interface to CPUID. On modern systems, it is chmod'd 0440, and its use is discouraged. Instead, since [http://lkml.indiana.edu/hypermail/linux/kernel/0801.3/2419.html at least 2.6.24] a [[sysfs]] interface has been supported; see <tt>/sys/devices/system/cpu//</tt>:<pre>[dumbledore](0) $ for i in /sys/devices/system/cpu/cpu0/cache//* /sys/devices/system/cpu/cpu0/topology/* ; do echo -n "`basename $i`: " && cat $i ; done		On [[Linux APIs\|Linux]], the <tt>/dev/cpuid(4)</tt> device provides an obsolete interface to CPUID. On modern systems, it is chmod'd 0440, and its use is discouraged. Instead, since [http://lkml.indiana.edu/hypermail/linux/kernel/0801.3/2419.html at least 2.6.24] a [[sysfs]] interface has been supported; see <tt>/sys/devices/system/cpu//</tt>:<pre>[dumbledore](0) $ for i in /sys/devices/system/cpu/cpu0/cache//* /sys/devices/system/cpu/cpu0/topology/* ; do echo -n "`basename $i`: " && cat $i ; done

Dank: /* CPUID and multiple processors */

2009-09-21T13:59:06Z

CPUID and multiple processors

@@ Line 24: / Line 24: @@
 * the process must be able to bind itself to a CPU (usually requiring root), or
 * the operating system must provide a world-readable interface (ie, the process never calls CPUID directly)
-On [[Linux APIs|Linux]], the <tt>/dev/cpuid(4)</tt> device provides an obsolete interface to CPUID. On modern systems, it is chmod'd 0440, and its use is discouraged. Instead, since [http://lkml.indiana.edu/hypermail/linux/kernel/0801.3/2419.html at least 2.6.24] a [[sysfs]] interface has been supported; see <tt>/sys/devices/system/cpu/*/</tt>.
+On [[Linux APIs|Linux]], the <tt>/dev/cpuid(4)</tt> device provides an obsolete interface to CPUID. On modern systems, it is chmod'd 0440, and its use is discouraged. Instead, since [http://lkml.indiana.edu/hypermail/linux/kernel/0801.3/2419.html at least 2.6.24] a [[sysfs]] interface has been supported; see <tt>/sys/devices/system/cpu/*/</tt>:<pre>[dumbledore](0) $ for i in /sys/devices/system/cpu/cpu0/cache/*/* /sys/devices/system/cpu/cpu0/topology/* ; do echo -n "`basename $i`: " && cat $i ; done
 ==See Also==

← Older revision		Revision as of 05:27, 3 November 2009
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	==See Also==		==See Also==
	* [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction" (2009-03)		* [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction" (2009-08)
	* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf AMD Publication 25481], "AMD CPUID Specification" (2008-04)		* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf AMD Publication 25481], "AMD CPUID Specification" (2008-04)

	[[Category: x86]]		[[Category: x86]]