CUDA - revision history

Dank: "65K" ?!

2019-08-15T01:33:54Z

"65K" ?!

← Older revision		Revision as of 01:33, 15 August 2019
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	===Streaming Multiprocessor===		===Streaming Multiprocessor===
	* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor\|Stream Processors]] (SPs).		* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor\|Stream Processors]] (SPs).
	** ~~8192~~ registers for compute capability <= 1.1, otherwise		** 8K registers for compute capability <= 1.1, otherwise
	** ~~16384~~ for compute capability <= 1.3, otherwise		** 16K for compute capability <= 1.3, otherwise
	** ~~32768~~ for compute capability <= 2.1, otherwise		** 32K for compute capability <= 2.1, otherwise
	** ~~65k~~ through at least compute capability 3.5		** 64K through at least compute capability 3.5
	* A group of threads which share a memory and can "synchronize their execution to coördinate accesses to memory" (use a [[barrier]]) form a '''block'''. Each thread has a ''threadId'' within its (three-dimensional) block.		* A group of threads which share a memory and can "synchronize their execution to coördinate accesses to memory" (use a [[barrier]]) form a '''block'''. Each thread has a ''threadId'' within its (three-dimensional) block.
	** For a block of dimensions <D<sub>x</sub>, D<sub>y</sub>, D<sub>z</sub>>, the threadId of the thread having index <x, y, z> is (x + y * D<sub>x</sub> + z * D<sub>y</sub> * D<sub>x</sub>).		** For a block of dimensions <D<sub>x</sub>, D<sub>y</sub>, D<sub>z</sub>>, the threadId of the thread having index <x, y, z> is (x + y * D<sub>x</sub> + z * D<sub>y</sub> * D<sub>x</sub>).

Dank: link to CC section when introducing compute capabilities

2019-08-15T01:31:19Z

link to CC section when introducing compute capabilities

← Older revision		Revision as of 01:31, 15 August 2019
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	nvidia 0000:07:00.0: setting latency timer to 64		nvidia 0000:07:00.0: setting latency timer to 64
	NVRM: loading NVIDIA UNIX x86_64 Kernel Module 190.53 Wed Dec 9 15:29:46 PST 2009</pre>		NVRM: loading NVIDIA UNIX x86_64 Kernel Module 190.53 Wed Dec 9 15:29:46 PST 2009</pre>
	Once the module is loaded, CUDA should be able to find the device. See [[CUDA#deviceQuery_Output\|below]] for sample outputs. Each device has a ~~'''~~compute capability~~'''~~, though this does not encompass all differentiated capabilities (see also <tt>deviceOverlap</tt> and <tt>canMapHostMemory</tt>...). Note that "emulation mode" has been removed as of CUDA Toolkit Version 3.1.		Once the module is loaded, CUDA should be able to find the device. See [[CUDA#deviceQuery_Output\|below]] for sample outputs. Each device has a [[CUDA#Compute_Capabilities\|compute capability]], though this does not encompass all differentiated capabilities (see also <tt>deviceOverlap</tt> and <tt>canMapHostMemory</tt>...). Note that "emulation mode" has been removed as of CUDA Toolkit Version 3.1.

	==CUDA model==		==CUDA model==

Dank: /* Compute Capabilities */

2019-08-15T01:29:28Z

Compute Capabilities

← Older revision		Revision as of 01:29, 15 August 2019
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	===Compute Capabilities===		===Compute Capabilities===
	The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been ~~backwards~~-compatible.		The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been fowards-compatible, though recent CUDA toolkits will not generate code for CC1 or 2.

	{\| border="1" class="wikitable"		{\| border="1" class="wikitable"

Dank: /* Compute Capabilities */

2019-08-15T01:27:39Z

Compute Capabilities

@@ Line 351: / Line 351: @@
 ** Indirect texture/surface support
 ** Extends generic addressing to include the const state space
 |-
 |}

Dank: /* Compute Capabilities */

2019-08-15T01:14:05Z

Compute Capabilities

← Older revision		Revision as of 01:14, 15 August 2019
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	\|64/2<br/>64/8		\|64/2<br/>64/8
	\|-		\|-
	\|~~Warp schedulers~~		\|Schedulers
	\|1		\|1
	\|1		\|1
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	\|2K		\|2K
	\|2K		\|2K
	\|2K		\|1K
	\|-		\|-
	\|Warps		\|Warps
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	\|64		\|64
	\|64		\|64
	\|64		\|32
	\|-		\|-
	\|Blocks		\|Blocks
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	\|64K		\|64K
	\|-		\|-
	\|~~Example chips~~		\|Examples
	\|G80		\|G80
	\|G9x		\|G9x

Dank: /* Compute Capabilities */

2019-08-15T01:11:51Z

Compute Capabilities

← Older revision		Revision as of 01:11, 15 August 2019
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	! 3.0 SMX		! 3.0 SMX
	! 3.5 SMX		! 3.5 SMX
			! 7.0 SM
			! 7.5 SM
	\|-		\|-
	\|CUDA cores		\|CUDA cores
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	\|192		\|192
	\|192		\|192
			\|64/32<br/>64/8
			\|64/2<br/>64/8
	\|-		\|-
	\|Warp schedulers		\|Warp schedulers
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	\|2		\|2
	\|2		\|2
			\|4
			\|4
	\|4		\|4
	\|4		\|4
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	\|2		\|2
	\|2		\|2
			\|1
			\|1
	\|-		\|-
	\|Threads		\|Threads
	\|768		\|768
	\|768		\|768
	\|~~1024~~		\|1K
	\|~~1024~~		\|1K
	\|1536		\|1536
	\|1536		\|1536
	\|~~2048~~		\|2K
	\|~~2048~~		\|2K
			\|2K
			\|2K
	\|-		\|-
	\|Warps		\|Warps
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	\|48		\|48
	\|48		\|48
			\|64
			\|64
	\|64		\|64
	\|64		\|64
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	\|8		\|8
	\|16		\|16
			\|16
			\|32
	\|16		\|16
	\|-		\|-
	\|32-bit ~~registers~~		\|32-bit regs
	\|~~8192~~		\|8K
	\|~~8192~~		\|8K
	\|~~16384~~		\|16K
	\|~~16384~~		\|16K
	\|~~32768~~		\|32K
	\|~~32768~~		\|32K
	\|~~65536~~		\|64K
	\|~~65536~~		\|64K
			\|64K
			\|64K
	\|-		\|-
	\|Example chips		\|Example chips
	\|		\|G80
	\|		\|G9x
	\|		\|GT21x
	\|		\|GT200
	\| ~~GF100~~		\|GF110
	\| ~~GF104/GF106/GF108~~		\|GF10x
	\| GK104		\|GK104
	\| GK110		\|GK110
			\|GV100
			\|TU10x
	\|-		\|-
	\|}		\|}

Dank: /* Compute Capabilities */

2019-08-14T11:56:41Z

Compute Capabilities

← Older revision		Revision as of 11:56, 14 August 2019
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	===Compute Capabilities===		===Compute Capabilities===
	The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been backwards-compatible.		The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been backwards-compatible.

	{\| border="1" class="wikitable"		{\| border="1" class="wikitable"
	! Resource		! Resource
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	\| GK110		\| GK110
	\|-		\|-
	}		\|}
	{\| border="1"		{\| border="1"
	! Revision		! Revision

Dank: kill const memory size column, add V100

2019-08-14T07:01:51Z

kill const memory size column, add V100

Show changes

Dank: /* deviceQuery info */

2019-08-12T11:17:01Z

deviceQuery info

← Older revision		Revision as of 11:17, 12 August 2019
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	* A run time limit is activated by default if the device is being used to drive a display.		* A run time limit is activated by default if the device is being used to drive a display.
	* Please feel free to [mailto:nickblack@acm.org send me output!]		* Please feel free to [mailto:nickblack@acm.org send me output!]


	{\| border="1"		{\| border="1"
	! Device name		! Device name

Dank: fix markup

2019-08-12T11:16:48Z

fix markup

← Older revision		Revision as of 11:16, 12 August 2019
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	* <tt>-X -v</tt> displays per-thread register usage		* <tt>-X -v</tt> displays per-thread register usage
	* <tt>-X -abi=no</tt> disables the PTX ABI, saving registers but taking away your stack		* <tt>-X -abi=no</tt> disables the PTX ABI, saving registers but taking away your stack
	* <tt>-dlcm={cg,cs,ca} modifies cache behavior for loads		* <tt>-dlcm={cg,cs,ca}</tt> modifies cache behavior for loads
	* <tt>-dscm={cw,cs} modifies cache behavior for stores		* <tt>-dscm={cw,cs}</tt> modifies cache behavior for stores
	===SDK's common.mk===		===SDK's common.mk===
	This assumes use of the SDK's common.mk, as recommended by the documentation.		This assumes use of the SDK's common.mk, as recommended by the documentation.