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File:Memoryhierarchy.png - revision history
2026-07-22T23:03:57Z
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Dank: Diagram (from Patterson & Hennessy's ''Computer Architecture: A Quantitative Approach'') of a hypothetical memory hierarchy's path from virtual address access to L2 cache access. 8K pages, direct-mapped 256-entry TLB, direct-mapped 8K L1 (64 byte lines),
2009-09-21T14:15:20Z
<p>Diagram (from Patterson & Hennessy's ''Computer Architecture: A Quantitative Approach'') of a hypothetical memory hierarchy's path from virtual address access to L2 cache access. 8K pages, direct-mapped 256-entry TLB, direct-mapped 8K L1 (64 byte lines), </p>
<p><b>New page</b></p><div>Diagram (from Patterson & Hennessy's ''Computer Architecture: A Quantitative Approach'') of a hypothetical memory hierarchy's path from virtual address access to L2 cache access. 8K pages, direct-mapped 256-entry TLB, direct-mapped 8K L1 (64 byte lines), direct-mapped 4M L2 (64 byte blocks), 64-bit virtual address, 40 bit physical address.</div>
Dank