Haswell - revision history

Dank at 13:22, 1 December 2012

2012-12-01T13:22:46Z

← Older revision		Revision as of 13:22, 1 December 2012
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	[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the SMT-split queue of [[Ivy Bridge]]. ]]		[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the SMT-split queue of [[Ivy Bridge]]. ]]
	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay"). Haswell supports [[AVX\|AVX2]] instructions (including the FMA set) on two ports, doubling both single and double-precision AVX floating point flops over [[Ivy Bridge]].

	[[File:Haswellexec.png\|right\|thumb\|Haswell employs an 8-wide ALU.]]		[[File:Haswellexec.png\|right\|thumb\|Haswell employs an 8-wide ALU.]]

Dank at 13:14, 1 December 2012

2012-12-01T13:14:46Z

← Older revision		Revision as of 13:14, 1 December 2012
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	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").

			[[File:Haswellexec.png\|right\|thumb\|Haswell employs an 8-wide ALU.]]
	==See Also==		==See Also==
	* "[http://www.anandtech.com/show/6355/intels-haswell-architecture Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel]", Anandtech, 2012-10-05		* "[http://www.anandtech.com/show/6355/intels-haswell-architecture Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel]", Anandtech, 2012-10-05

Dank at 13:12, 1 December 2012

2012-12-01T13:12:30Z

← Older revision		Revision as of 13:12, 1 December 2012
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	[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the split queue of [[Ivy Bridge]]. ]]		[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the SMT-split queue of [[Ivy Bridge]]. ]]
	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").

Dank at 13:11, 1 December 2012

2012-12-01T13:11:41Z

← Older revision		Revision as of 13:11, 1 December 2012
Line 1:		Line 1:
			[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the split queue of [[Ivy Bridge]]. ]]
	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").

Dank at 13:07, 1 December 2012

2012-12-01T13:07:41Z

← Older revision		Revision as of 13:07, 1 December 2012
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	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states and improvements throughout the associated chipset ("Shark Bay").		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").

	==See Also==		==See Also==

Dank at 13:06, 1 December 2012

2012-12-01T13:06:26Z

← Older revision		Revision as of 13:06, 1 December 2012
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	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction.		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states and improvements throughout the associated chipset ("Shark Bay").

	==See Also==		==See Also==

Dank at 13:01, 1 December 2012

2012-12-01T13:01:27Z

← Older revision		Revision as of 13:01, 1 December 2012
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	==See Also==		==See Also==
			* "[http://www.anandtech.com/show/6355/intels-haswell-architecture Intel's Haswell Architecture Analyzed: Building a New PC and a New Intel]", Anandtech, 2012-10-05
	* "[http://www.realworldtech.com/page.cfm?ArticleID=RWT021512050738 Analysis of Transactional Memory in Haswell]", Real World Technologies, 2012-02-15		* "[http://www.realworldtech.com/page.cfm?ArticleID=RWT021512050738 Analysis of Transactional Memory in Haswell]", Real World Technologies, 2012-02-15
	* "[http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/ Transactional Synchronization in Haswell]", Intel SDN, 2012-02-07		* "[http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/ Transactional Synchronization in Haswell]", Intel SDN, 2012-02-07
	[[CATEGORY: X86]]		[[CATEGORY: X86]]

Dank at 13:00, 1 December 2012

2012-12-01T13:00:40Z

← Older revision		Revision as of 13:00, 1 December 2012
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	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]].		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction.

	==See Also==		==See Also==

Dank: add real world tech link

2012-02-17T18:58:25Z

add real world tech link

← Older revision		Revision as of 18:58, 17 February 2012
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	==See Also==		==See Also==
			* "[http://www.realworldtech.com/page.cfm?ArticleID=RWT021512050738 Analysis of Transactional Memory in Haswell]", Real World Technologies, 2012-02-15
	* "[http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/ Transactional Synchronization in Haswell]", Intel SDN, 2012-02-07		* "[http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/ Transactional Synchronization in Haswell]", Intel SDN, 2012-02-07

	[[CATEGORY: X86]]		[[CATEGORY: X86]]

Dank: transactional mem in haswell

2012-02-08T20:50:37Z

transactional mem in haswell

← Older revision		Revision as of 20:50, 8 February 2012
Line 1:		Line 1:
	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013.		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]].

			==See Also==
			* "[http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/ Transactional Synchronization in Haswell]", Intel SDN, 2012-02-07

	[[CATEGORY: X86]]		[[CATEGORY: X86]]

← Older revision		Revision as of 13:22, 1 December 2012
Line 1:		Line 1:
	[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the SMT-split queue of [[Ivy Bridge]]. ]]		[[File:Haswellfrontend.png\|right\|thumb\|Haswell frontend. Note the unified decode queue compared to the SMT-split queue of [[Ivy Bridge]]. ]]
	Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay").		Haswell follows [[Ivy Bridge]], the die-shrunk "[[Tick-Tock\|Tock]]" of Intel's [[Nehalem]]. It will be manufactured on a 22nm process, and is scheduled to be released in Q1 2013. Haswell will feature [[transactional memory]], and represents a major step forward in power reduction, largely through new [[ACPI]] sleep states ("S0ix states") and improvements throughout the associated chipset ("Shark Bay"). Haswell supports [[AVX\|AVX2]] instructions (including the FMA set) on two ports, doubling both single and double-precision AVX floating point flops over [[Ivy Bridge]].

	[[File:Haswellexec.png\|right\|thumb\|Haswell employs an 8-wide ALU.]]		[[File:Haswellexec.png\|right\|thumb\|Haswell employs an 8-wide ALU.]]