Ivy Bridge - revision history

Dank: /* Architecture */

2011-10-18T22:26:17Z

Architecture

← Older revision		Revision as of 22:26, 18 October 2011
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	A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support. Ivy Bridge is expected to continue making use of the LGA1155 socket interface introduced with Sandy Bridge.		A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support. Ivy Bridge is expected to continue making use of the LGA1155 socket interface introduced with Sandy Bridge.
	==Architecture==		==Architecture==
			[[File:Smep.jpeg\|right\|thumb\|IDF 2011 slide on SMEP]]
	* The [[RDRAND]] instruction is made available on Ivy Bridge processors containing Bull Mountain hardware.		* The [[RDRAND]] instruction is made available on Ivy Bridge processors containing Bull Mountain hardware.
	* Supervisory Mode Execution Protection (SMEP) prohibits ring 0 code from executing memory writable by other rings		* Supervisory Mode Execution Protection (SMEP) prohibits ring 0 code from executing memory writable by other rings

	==Microarchitecture==		==Microarchitecture==
	Microarchitecture is expected to be similar to that of [[Sandy Bridge]].		Microarchitecture is expected to be similar to that of [[Sandy Bridge]].

Dank at 22:25, 18 October 2011

2011-10-18T22:25:09Z

← Older revision		Revision as of 22:25, 18 October 2011
Line 1:		Line 1:
	A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support. Ivy Bridge is expected to continue making use of the LGA1155 socket interface introduced with Sandy Bridge.		A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support. Ivy Bridge is expected to continue making use of the LGA1155 socket interface introduced with Sandy Bridge.
	==Architecture==		==Architecture==
			* The [[RDRAND]] instruction is made available on Ivy Bridge processors containing Bull Mountain hardware.
			* Supervisory Mode Execution Protection (SMEP) prohibits ring 0 code from executing memory writable by other rings
	==Microarchitecture==		==Microarchitecture==
	Microarchitecture is expected to be similar to that of [[Sandy Bridge]].		Microarchitecture is expected to be similar to that of [[Sandy Bridge]].
Line 6:		Line 8:
	==Processor Support==		==Processor Support==
	Ivy Bridge will introduce the "Panther Point" 7-series PCH (Platform Controller Hub), and the second-tier "Patsburg" X79 (this latter will use DMI rather than QPI). Native USB 3.0 and [[PCIe\|PCIe 3.0]] support is expected on-chip.		Ivy Bridge will introduce the "Panther Point" 7-series PCH (Platform Controller Hub), and the second-tier "Patsburg" X79 (this latter will use DMI rather than QPI). Native USB 3.0 and [[PCIe\|PCIe 3.0]] support is expected on-chip.

			==See Also==
			* "[http://www.hardwaresecrets.com/article/Inside-the-Intel-Ivy-Bridge-Microarchitecture/1397 Inside the Intel Ivy Bridge Microarchitecture]" at www.hardwaresecrets.com
	[[CATEGORY: x86]]		[[CATEGORY: x86]]
	[[CATEGORY: Hardware]]		[[CATEGORY: Hardware]]

Dank: conform to the sandy bridge implicit template

2011-09-21T08:36:00Z

conform to the sandy bridge implicit template

← Older revision		Revision as of 08:36, 21 September 2011
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	==Microarchitecture==		==Microarchitecture==
	Microarchitecture is expected to be similar to that of [[Sandy Bridge]].		Microarchitecture is expected to be similar to that of [[Sandy Bridge]].
	==~~Chipset~~==		==Branding/Differentiation==
			==Processor Support==
	Ivy Bridge will introduce the "Panther Point" 7-series PCH (Platform Controller Hub), and the second-tier "Patsburg" X79 (this latter will use DMI rather than QPI). Native USB 3.0 and [[PCIe\|PCIe 3.0]] support is expected on-chip.		Ivy Bridge will introduce the "Panther Point" 7-series PCH (Platform Controller Hub), and the second-tier "Patsburg" X79 (this latter will use DMI rather than QPI). Native USB 3.0 and [[PCIe\|PCIe 3.0]] support is expected on-chip.
	[[CATEGORY: x86]]		[[CATEGORY: x86]]
	[[CATEGORY: Hardware]]		[[CATEGORY: Hardware]]

Dank at 12:16, 9 August 2011

2011-08-09T12:16:47Z

← Older revision		Revision as of 12:16, 9 August 2011
Line 1:		Line 1:
	A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support.		A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support. Ivy Bridge is expected to continue making use of the LGA1155 socket interface introduced with Sandy Bridge.
	==Architecture==		==Architecture==
	==Microarchitecture==		==Microarchitecture==
	Microarchitecture is expected to be similar to that of [[Sandy Bridge]].		Microarchitecture is expected to be similar to that of [[Sandy Bridge]].
	==Chipset==		==Chipset==
			Ivy Bridge will introduce the "Panther Point" 7-series PCH (Platform Controller Hub), and the second-tier "Patsburg" X79 (this latter will use DMI rather than QPI). Native USB 3.0 and [[PCIe\|PCIe 3.0]] support is expected on-chip.
	[[CATEGORY: x86]]		[[CATEGORY: x86]]
	[[CATEGORY: Hardware]]		[[CATEGORY: Hardware]]

Dank at 12:11, 9 August 2011

2011-08-09T12:11:35Z

← Older revision		Revision as of 12:11, 9 August 2011
Line 1:		Line 1:
	A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support.		A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support.
	==Architecture==		==Architecture==
	==Microarchitecture==		==Microarchitecture==
			Microarchitecture is expected to be similar to that of [[Sandy Bridge]].
	==Chipset==		==Chipset==

	[[CATEGORY: x86]]		[[CATEGORY: x86]]
	[[CATEGORY: Hardware]]		[[CATEGORY: Hardware]]

Dank at 12:10, 9 August 2011

2011-08-09T12:10:16Z

← Older revision		Revision as of 12:10, 9 August 2011
Line 1:		Line 1:
	A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. It is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support.		A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support.
	==Architecture==		==Architecture==
	==Microarchitecture==		==Microarchitecture==
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	[[CATEGORY: x86]]		[[CATEGORY: x86]]
	[[CATEGORY: Hardware		[[CATEGORY: Hardware]]

Dank at 12:09, 9 August 2011

2011-08-09T12:09:20Z

← Older revision		Revision as of 12:09, 9 August 2011
Line 1:		Line 1:
	A 22nm update to [[Sandy Bridge]]. ~~Not yet released~~.		A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. It is expected to support [[PCIe\|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL\|OpenCL 1.1]] support.
			==Architecture==
			==Microarchitecture==
			==Chipset==

	[[CATEGORY: x86]]		[[CATEGORY: x86]]
	[[CATEGORY: Hardware]]		[[CATEGORY: Hardware

Dank: Created page with 'A 22nm update to Sandy Bridge. Not yet released. CATEGORY: x86 CATEGORY: Hardware'

2011-01-12T07:52:21Z

Created page with 'A 22nm update to Sandy Bridge. Not yet released. CATEGORY: x86 CATEGORY: Hardware'

New page

A 22nm update to [[Sandy Bridge]]. Not yet released.
[[CATEGORY: x86]]
[[CATEGORY: Hardware]]