Nehalem - revision history

Dank at 16:32, 25 February 2012

2012-02-25T16:32:50Z

← Older revision		Revision as of 16:32, 25 February 2012
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			[[File:Nehalem.svg\|thumb\|right\|Nehalem-EP NUMA arrangement]]
	[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]		[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]
	[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]		[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]

Dank at 09:13, 12 January 2011

2011-01-12T09:13:26Z

← Older revision		Revision as of 09:13, 12 January 2011
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	[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]		[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]
	[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]		[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]
			The successor of [[Core 2]], and predecessor of [[Sandy Bridge]].
	* Move to 133MHz [[QPI (Quick Path Interconnect)]], against which the CPU clock is multiplied		* Move to 133MHz [[QPI (Quick Path Interconnect)]], against which the CPU clock is multiplied
	* Reintroduction of [[SMP on x86#SMT\|SMT (HyperThreading)]]		* Reintroduction of [[SMP on x86#SMT\|SMT (HyperThreading)]]

Dank at 07:53, 12 January 2011

2011-01-12T07:53:33Z

← Older revision		Revision as of 07:53, 12 January 2011
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	* Be sure to use register parameter-passing conventions, not the stack, to avoid stalls on store-forward of high-latency floating point stores.		* Be sure to use register parameter-passing conventions, not the stack, to avoid stalls on store-forward of high-latency floating point stores.
	* Peak issue rate of 1 128-bit load and 1 128-bit store per cycle.		* Peak issue rate of 1 128-bit load and 1 128-bit store per cycle.
			* [[Turbo Boost]] in 133MHz increments
	==See Also==		==See Also==
	* The Dark Knight's [http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448 AnandTech] article, 2008-11-03.		* The Dark Knight's [http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448 AnandTech] article, 2008-11-03.
	[[Category: x86]]		[[Category: x86]]
	[[CATEGORY: Hardware]]		[[CATEGORY: Hardware]]

Dank at 19:35, 22 March 2010

2010-03-22T19:35:19Z

← Older revision		Revision as of 19:35, 22 March 2010
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	* The Dark Knight's [http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448 AnandTech] article, 2008-11-03.		* The Dark Knight's [http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448 AnandTech] article, 2008-11-03.
	[[Category: x86]]		[[Category: x86]]
			[[CATEGORY: Hardware]]

Dank at 07:41, 17 March 2010

2010-03-17T07:41:54Z

← Older revision		Revision as of 07:41, 17 March 2010
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	[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]		[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]
	[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]		[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]
			* Move to 133MHz [[QPI (Quick Path Interconnect)]], against which the CPU clock is multiplied
	* Reintroduction of [[SMP on x86#SMT\|SMT (HyperThreading)]]		* Reintroduction of [[SMP on x86#SMT\|SMT (HyperThreading)]]
	* Store-forwarding aliasing issue on 4k strides.		* Store-forwarding aliasing issue on 4k strides.
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	* Forwarding results between integer, integer SIMD, and FP units adds latency compared to forwards within the domain.		* Forwarding results between integer, integer SIMD, and FP units adds latency compared to forwards within the domain.
	* One register may be written per cycle.		* One register may be written per cycle.
	* Move to [[QPI (Quick Path Interconnect)]]		* 48 load buffers (up from 32), 32 store buffers (up from 20), 10 fill buffers.
	* 48 load buffers, 32 store buffers, 10 fill buffers.
	* 36 reservation stations (up from 32), 128 ROB entries (up from 96).		* 36 reservation stations (up from 32), 128 ROB entries (up from 96).
	* Calltrace cache of 16 entries.		* Calltrace cache of 16 entries.
Line 21:		Line 21:
	* Be sure to use register parameter-passing conventions, not the stack, to avoid stalls on store-forward of high-latency floating point stores.		* Be sure to use register parameter-passing conventions, not the stack, to avoid stalls on store-forward of high-latency floating point stores.
	* Peak issue rate of 1 128-bit load and 1 128-bit store per cycle.		* Peak issue rate of 1 128-bit load and 1 128-bit store per cycle.
			==See Also==
			* The Dark Knight's [http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448 AnandTech] article, 2008-11-03.
	[[Category: x86]]		[[Category: x86]]

Dank at 07:35, 17 March 2010

2010-03-17T07:35:05Z

← Older revision		Revision as of 07:35, 17 March 2010
Line 9:		Line 9:
	* Forwarding results between integer, integer SIMD, and FP units adds latency compared to forwards within the domain.		* Forwarding results between integer, integer SIMD, and FP units adds latency compared to forwards within the domain.
	* One register may be written per cycle.		* One register may be written per cycle.
			* Move to [[QPI (Quick Path Interconnect)]]
	* 48 load buffers, 32 store buffers, 10 fill buffers.		* 48 load buffers, 32 store buffers, 10 fill buffers.
	* 36 reservation stations (up from 32), 128 ROB entries (up from 96).		* 36 reservation stations (up from 32), 128 ROB entries (up from 96).

Dank at 07:33, 17 March 2010

2010-03-17T07:33:46Z

← Older revision		Revision as of 07:33, 17 March 2010
Line 20:		Line 20:
	* Be sure to use register parameter-passing conventions, not the stack, to avoid stalls on store-forward of high-latency floating point stores.		* Be sure to use register parameter-passing conventions, not the stack, to avoid stalls on store-forward of high-latency floating point stores.
	* Peak issue rate of 1 128-bit load and 1 128-bit store per cycle.		* Peak issue rate of 1 128-bit load and 1 128-bit store per cycle.
			[[Category: x86]]

Dank at 07:31, 17 March 2010

2010-03-17T07:31:17Z

← Older revision		Revision as of 07:31, 17 March 2010
Line 1:		Line 1:
	[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]		[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]
	[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]		[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]
	* Reintroduction of SMT		* Reintroduction of [[SMP on x86#SMT\|SMT (HyperThreading)]]
	* Store-forwarding aliasing issue on 4k strides.		* Store-forwarding aliasing issue on 4k strides.
	* Double-pumped FP SSE + integer SSE/x87 + load + store units		* Double-pumped FP SSE + integer SSE/x87 + load + store units

Dank at 07:30, 17 March 2010

2010-03-17T07:30:48Z

← Older revision		Revision as of 07:30, 17 March 2010
Line 1:		Line 1:
	[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]		[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]
	[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]		[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]
			* Reintroduction of SMT
	* Store-forwarding aliasing issue on 4k strides.		* Store-forwarding aliasing issue on 4k strides.
	* Double-pumped FP SSE + integer SSE/x87 + load + store units		* Double-pumped FP SSE + integer SSE/x87 + load + store units

Dank at 07:30, 17 March 2010

2010-03-17T07:30:09Z

← Older revision		Revision as of 07:30, 17 March 2010
Line 9:		Line 9:
	* One register may be written per cycle.		* One register may be written per cycle.
	* 48 load buffers, 32 store buffers, 10 fill buffers.		* 48 load buffers, 32 store buffers, 10 fill buffers.
	* 36 reservation stations, 96 ROB entries.		* 36 reservation stations (up from 32), 128 ROB entries (up from 96).
	* Calltrace cache of 16 entries.		* Calltrace cache of 16 entries.
	* 2-way loop end BTB for every 16 bytes, 4-way general BTB.		* 2-way loop end BTB for every 16 bytes, 4-way general BTB.

← Older revision		Revision as of 16:32, 25 February 2012
Line 1:		Line 1:
			[[File:Nehalem.svg\|thumb\|right\|Nehalem-EP NUMA arrangement]]
	[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]		[[File:IAmNehalem.jpg\|thumb\|right\|Ehyeh asher ehyeh]]
	[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]		[[File:Intel Nehalem arch.png\|thumb\|right\|Nehalem microarchitecture]]