SMP on x86 - revision history

Dank: /* See also */

2010-03-22T19:35:44Z

Dank: /* SMT */

2010-03-17T07:48:44Z

SMT

← Older revision		Revision as of 07:48, 17 March 2010
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	** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).		** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).
	** Pentium-M and Celerons usually lack SMT.		** Pentium-M and Celerons usually lack SMT.
	* ~~Resources~~ are either split or shared between logical cores:		* Unduplicated resources are either split or shared between logical cores:
	** Shared: reservation stations, data caches		** Shared: reservation stations, data caches
	** Split: reorder buffers, load/store buffers		** Split: reorder buffers, load/store buffers
			** Duplicated: registers
			* No programmable priority control exported, no implicit priorities defined

	==Intel MP IDs==		==Intel MP IDs==

Dank: /* SMT */

2010-03-17T07:42:13Z

SMT

← Older revision		Revision as of 07:42, 17 March 2010
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	* Resources are either split or shared between logical cores:		* Resources are either split or shared between logical cores:
	** Shared: reservation stations, data caches		** Shared: reservation stations, data caches
	** Split: reorder buffers		** Split: reorder buffers, load/store buffers

	==Intel MP IDs==		==Intel MP IDs==

Dank: /* SMT */

2010-03-17T07:33:22Z

SMT

← Older revision		Revision as of 07:33, 17 March 2010
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	** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).		** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).
	** Pentium-M and Celerons usually lack SMT.		** Pentium-M and Celerons usually lack SMT.
			* Resources are either split or shared between logical cores:
			** Shared: reservation stations, data caches
			** Split: reorder buffers

	==Intel MP IDs==		==Intel MP IDs==

Dank: /* Intel MP IDs */

2009-10-27T13:34:23Z

Intel MP IDs

← Older revision		Revision as of 13:34, 27 October 2009
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	*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors		*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors
	*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore		*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore
	* APIC ID is formed of SMT_ID\|CORE_ID\|PACKAGE_ID, having widths defined by the packaging data		* APIC ID is formed of SMT_ID\|CORE_ID\|PACKAGE_ID, having widths defined by the packaging data:
	** SMT_ID is 0 bits on a non-HyperThreaded processor.		** SMT_ID is 0 bits on a non-HyperThreaded processor.
	** CORE_ID is 0 bits on a unicore package		** CORE_ID is 0 bits on a unicore package

Dank: /* Intel MP IDs */

2009-10-27T13:32:27Z

Intel MP IDs

← Older revision		Revision as of 13:32, 27 October 2009
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	==Intel MP IDs==		==Intel MP IDs==
	* Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID		* Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID
	** The initial APIC ID can be retrieved via [[cpuid]], as can~~...~~		** The initial APIC ID can be retrieved via [[cpuid]], as can packaging data:
	*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured		*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured
	*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured		*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured
	*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel		*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel
	*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors		*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors
			*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore
			* APIC ID is formed of SMT_ID\|CORE_ID\|PACKAGE_ID, having widths defined by the packaging data
			** SMT_ID is 0 bits on a non-HyperThreaded processor.
			** CORE_ID is 0 bits on a unicore package
			** All remaining bits are devoted to PACKAGE_ID

	==Interrupts==		==Interrupts==

Dank: /* Intel MP IDs */

2009-10-27T13:28:58Z

Intel MP IDs

← Older revision		Revision as of 13:28, 27 October 2009
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	==Intel MP IDs==		==Intel MP IDs==
	* Each logical processor is assigned a unique (but not necessarily sequential) identifier at boot, the APIC ID		* Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID
	** The initial APIC ID can be retrieved via [[cpuid]], as can...		** The initial APIC ID can be retrieved via [[cpuid]], as can...
	*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured		*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured

Dank at 13:27, 27 October 2009

2009-10-27T13:27:48Z

← Older revision		Revision as of 13:27, 27 October 2009
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	** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).		** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).
	** Pentium-M and Celerons usually lack SMT.		** Pentium-M and Celerons usually lack SMT.

			==Intel MP IDs==
			* Each logical processor is assigned a unique (but not necessarily sequential) identifier at boot, the APIC ID
			** The initial APIC ID can be retrieved via [[cpuid]], as can...
			*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured
			*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured
			*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel
			*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors

	==Interrupts==		==Interrupts==

Dank at 13:20, 27 October 2009

2009-10-27T13:20:27Z

← Older revision		Revision as of 13:20, 27 October 2009
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	* The [[cpuid]] instruction can interrogate each processing unit		* The [[cpuid]] instruction can interrogate each processing unit
	* [[Cpuset\|CPUsets]]		* [[Cpuset\|CPUsets]]
			* "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network
	[[Category: x86]]		[[Category: x86]]

Dank: /* Discovery */

2009-10-27T11:26:18Z

Discovery

← Older revision		Revision as of 11:26, 27 October 2009
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	[recombinator](0) $ </pre>		[recombinator](0) $ </pre>
	==Discovery==		==Discovery==
	* ACPI's MADT table can supply multiprocessor configuration, and is usually used if present		* [[ACPI]]'s MADT table can supply multiprocessor configuration, and is usually used if present
	* MP Table. The FreeBSD program <tt>mptable(1)</tt> can dump this:		* MP Table. The FreeBSD program <tt>mptable(1)</tt> can dump this:
	<pre>[bryhlath](0) $ sudo mptable		<pre>[bryhlath](0) $ sudo mptable

← Older revision		Revision as of 19:35, 22 March 2010
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	* "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network		* "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network
	[[Category: x86]]		[[Category: x86]]
			[[CATEGORY: Hardware]]