VEX - revision history

Dank at 13:43, 12 January 2011

2011-01-12T13:43:35Z

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 * Aside from explicitly aligned [[SSE]] load and store instructions, VEX does not require aligned memory operands
 ** This is different from [[SSE]], where the vast majority of instructions require alignment
 ==Sources==
 * "[http://www.ragestorm.net/blogs/?p=145 It's Vexed]", Insanely Low-Level, 2009-11-17

Dank at 13:34, 12 January 2011

2011-01-12T13:34:30Z

← Older revision		Revision as of 13:34, 12 January 2011
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	==Prefix viz x86==		==Prefix viz x86==
	The C4 and C5 bytes were traditionally used for LES (Load Extra Segment) and LDS (Load Data Segment) instructions. These are unavailable under x86's long mode, and thus C4/C5 clearly indicate VEX instructions in 64-bit programs. In 32-bit mode, the second byte is used to differentiate a LES/LDS from a VEX-encoded instruction. VEX is disabled in virtual-8086 or real mode, due to [http://en.wikipedia.org/wiki/Virtual_DOS_machine NTDVM's] use of 0xC4+0xC0 as a trap instruction. Such are the costs of backwards compatibility.		The C4 and C5 bytes were traditionally used for LES (Load Extra Segment) and LDS (Load Data Segment) instructions. These are unavailable under x86's long mode, and thus C4/C5 clearly indicate VEX instructions in 64-bit programs. In 32-bit mode, the second byte is used to differentiate a LES/LDS from a VEX-encoded instruction. VEX is disabled in virtual-8086 or real mode, due to [http://en.wikipedia.org/wiki/Virtual_DOS_machine NTDVM's] use of 0xC4+0xC0 as a trap instruction. Such are the costs of backwards compatibility.
			==General properties==
			* The majority of the [[SSE]] instruction sets through SSE5, including [[AES-NI]], have VEX equivalents.
			* Aside from explicitly aligned [[SSE]] load and store instructions, VEX does not require aligned memory operands
			** This is different from [[SSE]], where the vast majority of instructions require alignment
	==Sources==		==Sources==
	* "[http://www.ragestorm.net/blogs/?p=145 It's Vexed]", Insanely Low-Level, 2009-11-17		* "[http://www.ragestorm.net/blogs/?p=145 It's Vexed]", Insanely Low-Level, 2009-11-17

Dank: Created page with 'The Vector Extensions instruction encoding was introduced along with AVX in Sandy Bridge and Bulldozer processors. It makes use of C4 and C5 bytes to indicate a 3-byt...'

2011-01-12T09:09:16Z

Created page with 'The Vector Extensions instruction encoding was introduced along with AVX in Sandy Bridge and Bulldozer processors. It makes use of C4 and C5 bytes to indicate a 3-byt...'

New page

The Vector Extensions instruction encoding was introduced along with [[AVX]] in [[Sandy Bridge]] and [[Bulldozer]] processors. It makes use of C4 and C5 bytes to indicate a 3-byte or 2-byte, respectively, VEX prefix.

==Prefix viz x86==
The C4 and C5 bytes were traditionally used for LES (Load Extra Segment) and LDS (Load Data Segment) instructions. These are unavailable under x86's long mode, and thus C4/C5 clearly indicate VEX instructions in 64-bit programs. In 32-bit mode, the second byte is used to differentiate a LES/LDS from a VEX-encoded instruction. VEX is disabled in virtual-8086 or real mode, due to [http://en.wikipedia.org/wiki/Virtual_DOS_machine NTDVM's] use of 0xC4+0xC0 as a trap instruction. Such are the costs of backwards compatibility.
==Sources==
* "[http://www.ragestorm.net/blogs/?p=145 It's Vexed]", Insanely Low-Level, 2009-11-17
* "[http://software.intel.com/en-us/blogs/2009/01/29/recent-intelr-avx-architectural-changes/ Recent Intel AVX Architecture Changes]", Intel Software Network, 2009-01-29
* "[http://software.intel.com/en-us/avx/ Intel Advanced Vector Extensions Programming Reference]", Intel document 319433-009, December 2010
* "[http://www.agner.org/optimize/blog/read.php?i=25 Stop the Instruction Set War]", Agner Fog's CPU Blog, 2009-12-05
[[CATEGORY: x86]]