Winbond - revision history

Dank: /* W25N01GVxxIG/IT */

2019-03-29T07:23:16Z

W25N01GVxxIG/IT

← Older revision		Revision as of 07:23, 29 March 2019
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	The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.		The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.

	The device has JEDEC Manufacturer ID 0xEF and ~~evice~~ ID 0xAA21.		The device has JEDEC Manufacturer ID 0xEF and Device ID 0xAA21.

	Bad blocks are marked at the factory with a non-0xff byte as their first byte, and a non-0xff byte as the first byte of the first page's Spare Area (i.e. all blocks marked with 0xff as their first byte, and as the first byte of the first page's Spare Area, are considered good). Before executing the first program or erase instruction, pages ought be inspected, and added to the LUT if necessary.		Bad blocks are marked at the factory with a non-0xff byte as their first byte, and a non-0xff byte as the first byte of the first page's Spare Area (i.e. all blocks marked with 0xff as their first byte, and as the first byte of the first page's Spare Area, are considered good). Before executing the first program or erase instruction, pages ought be inspected, and added to the LUT if necessary.

Dank: /* W25N01GVxxIG/IT */

2019-03-29T07:16:51Z

W25N01GVxxIG/IT

← Older revision		Revision as of 07:16, 29 March 2019
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	===[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]===		===[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]===
	A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected ~~bits~~ are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).		A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bytes are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).

	The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.		The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.

Dank: /* Instructions */

2019-03-29T06:50:52Z

Instructions

← Older revision		Revision as of 06:50, 29 March 2019
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	* 0x34 -- QuadRandomLoadProgramData. RandomLoadProgramData using 4 pins for data transfer		* 0x34 -- QuadRandomLoadProgramData. RandomLoadProgramData using 4 pins for data transfer
	* 0x10 -- ProgramExecute. 8 dummy clocks followed by 2-byte page address. The data buffer is written to the page.		* 0x10 -- ProgramExecute. 8 dummy clocks followed by 2-byte page address. The data buffer is written to the page.
			** Pages must be written sequentially within a block!
	* 0x13 -- PageDataRead. 8 dummy clocks followed by 2-byte page address. The data buffer is filled from the page.		* 0x13 -- PageDataRead. 8 dummy clocks followed by 2-byte page address. The data buffer is filled from the page.
	** If OTP is enabled, page addresses 0x0--0xb are remapped to the Unique ID Page, Parameter Page, and 10 OTP pages		** If OTP is enabled, page addresses 0x0--0xb are remapped to the Unique ID Page, Parameter Page, and 10 OTP pages

Dank: /* Instructions */

2019-03-29T06:32:32Z

Instructions

← Older revision		Revision as of 06:32, 29 March 2019
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	====Instructions====		====Instructions====
	27 instructions are supported. Instruction read is initiated on the falling edge of /CS, and completion indicated by the rising edge. Write, Program, and Erase instructions must drive CS high on a byte boundary (8*n CLK cycles following /CS falling); this is relevant when using Dual- or Quad-SPI (where a byte requires 4 or 2 rather than 8 clocks). Most instructions are ignored when the BUSY bit of SR3 is set.		27 instructions are supported, generally compatible with the SpiFlash NOR command set. Instruction read is initiated on the falling edge of /CS, and completion indicated by the rising edge. Write, Program, and Erase instructions must drive CS high on a byte boundary (8*n CLK cycles following /CS falling); this is relevant when using Dual- or Quad-SPI (where a byte requires 4 or 2 rather than 8 clocks). Most instructions are ignored when the BUSY bit of SR3 is set.
	* 0xFF -- RESET. Data corruption can result if RESET is issued while BUSY is high.		* 0xFF -- RESET. Data corruption can result if RESET is issued while BUSY is high.
	* 0x9F -- ReadJEDEC, returns 0xEFAA21		* 0x9F -- ReadJEDEC, returns 0xEFAA21

Dank at 06:31, 29 March 2019

2019-03-29T06:31:49Z

← Older revision		Revision as of 06:31, 29 March 2019
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	[https://www.winbond.com/hq/ Winbond] of Taiwan manufactures semiconductor devices, including flash storage.		[https://www.winbond.com/hq/ Winbond] of Taiwan manufactures semiconductor devices, including flash storage.

	==[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]==		==Serial SLC NAND Memory==
			Product family 25N.

			===[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]===
	A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).		A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).

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	Bad blocks are marked at the factory with a non-0xff byte as their first byte, and a non-0xff byte as the first byte of the first page's Spare Area (i.e. all blocks marked with 0xff as their first byte, and as the first byte of the first page's Spare Area, are considered good). Before executing the first program or erase instruction, pages ought be inspected, and added to the LUT if necessary.		Bad blocks are marked at the factory with a non-0xff byte as their first byte, and a non-0xff byte as the first byte of the first page's Spare Area (i.e. all blocks marked with 0xff as their first byte, and as the first byte of the first page's Spare Area, are considered good). Before executing the first program or erase instruction, pages ought be inspected, and added to the LUT if necessary.

	===Packages===		====Packages====
	* 8-pad WSON 8x6mm (package code ZE)		* 8-pad WSON 8x6mm (package code ZE)
	* 16-pin SOIC 300-mil (package code SF)		* 16-pin SOIC 300-mil (package code SF)
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	* 4x6 24-ball 8x6mm TFBGA (package code TC)		* 4x6 24-ball 8x6mm TFBGA (package code TC)

	===Lines===		====Lines====
	* CLK serial clock input		* CLK serial clock input
	* /CS chip select input		* /CS chip select input
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	Data is written on the rising edge of CLK, and read on the falling edge.		Data is written on the rising edge of CLK, and read on the falling edge.

	===Status Registers===		====Status Registers====
	Used with the ReadStatusRegister and WriteStatusRegister commands. Factory defaults are 1 for the 4 BP bits, TB, and ECC-E, and 0 for all other bits (though this can be changed via OTP locking).		Used with the ReadStatusRegister and WriteStatusRegister commands. Factory defaults are 1 for the 4 BP bits, TB, and ECC-E, and 0 for all other bits (though this can be changed via OTP locking).
	* Protection Register (SR1)		* Protection Register (SR1)
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	** B0: Busy, set to 1 while instructions are not being accepted following many instructions		** B0: Busy, set to 1 while instructions are not being accepted following many instructions

	===Instructions===		====Instructions====
	27 instructions are supported. Instruction read is initiated on the falling edge of /CS, and completion indicated by the rising edge. Write, Program, and Erase instructions must drive CS high on a byte boundary (8*n CLK cycles following /CS falling); this is relevant when using Dual- or Quad-SPI (where a byte requires 4 or 2 rather than 8 clocks). Most instructions are ignored when the BUSY bit of SR3 is set.		27 instructions are supported. Instruction read is initiated on the falling edge of /CS, and completion indicated by the rising edge. Write, Program, and Erase instructions must drive CS high on a byte boundary (8*n CLK cycles following /CS falling); this is relevant when using Dual- or Quad-SPI (where a byte requires 4 or 2 rather than 8 clocks). Most instructions are ignored when the BUSY bit of SR3 is set.
	* 0xFF -- RESET. Data corruption can result if RESET is issued while BUSY is high.		* 0xFF -- RESET. Data corruption can result if RESET is issued while BUSY is high.

Dank: /* Instructions */

2019-03-29T06:30:18Z

Instructions

← Older revision		Revision as of 06:30, 29 March 2019
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	===Instructions===		===Instructions===
	27 instructions are supported. Instruction read is initiated on the falling edge of /CS, and completion indicated by the rising edge. Write, Program, and Erase instructions must drive CS high on a byte boundary (8*n CLK cycles following /CS falling); this is relevant when using Quad-SPI (where a byte requires 2 rather than 8 clocks). Most instructions are ignored when the BUSY bit of SR3 is set.		27 instructions are supported. Instruction read is initiated on the falling edge of /CS, and completion indicated by the rising edge. Write, Program, and Erase instructions must drive CS high on a byte boundary (8*n CLK cycles following /CS falling); this is relevant when using Dual- or Quad-SPI (where a byte requires 4 or 2 rather than 8 clocks). Most instructions are ignored when the BUSY bit of SR3 is set.
	* 0xFF -- RESET. Data corruption can result if RESET is issued while BUSY is high.		* 0xFF -- RESET. Data corruption can result if RESET is issued while BUSY is high.
	* 0x9F -- ReadJEDEC, returns 0xEFAA21		* 0x9F -- ReadJEDEC, returns 0xEFAA21

Dank: /* W25N01GVxxIG/IT */

2019-03-29T06:29:14Z

W25N01GVxxIG/IT

@@ Line 2: / Line 2: @@
 ==[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]==
-A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte.
+A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).
 The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.
 ===Packages===
@@ Line 30: / Line 34: @@
 Data is written on the rising edge of CLK, and read on the falling edge.
-===Registers===
+===Status Registers===
-Used with the ReadStatusRegister and WriteStatusRegister commands:
+Used with the ReadStatusRegister and WriteStatusRegister commands. Factory defaults are 1 for the 4 BP bits, TB, and ECC-E, and 0 for all other bits (though this can be changed via OTP locking).
 * Protection Register (SR1)
 ** MSB: Status register protect 0
@@ Line 66: / Line 70: @@
 ===Instructions===
-instructions are supported. Instruction read is initiated on the falling edge of /CS, and completed on the rising edge (8 clocks later). Write, Program, and Erase instructions must complete on a byte boundary (rising /CS), and most instructions are ignored when the BUSY bit of SR3 is set.
+instructions are supported. Instruction read is initiated on the falling edge of /CS, and completion indicated by the rising edge. Write, Program, and Erase instructions must drive CS high on a byte boundary (8*n CLK cycles following /CS falling); this is relevant when using Quad-SPI (where a byte requires 2 rather than 8 clocks). Most instructions are ignored when the BUSY bit of SR3 is set.

Dank: /* W25N01GVxxIG/IT */

2019-03-29T05:37:20Z

W25N01GVxxIG/IT

← Older revision		Revision as of 05:37, 29 March 2019
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	** B1: Write-enabled latch, set to 1 following WriteEnable instruction, set to 0 following many instructions		** B1: Write-enabled latch, set to 1 following WriteEnable instruction, set to 0 following many instructions
	** B0: Busy, set to 1 while instructions are not being accepted following many instructions		** B0: Busy, set to 1 while instructions are not being accepted following many instructions

			===Instructions===
			27 instructions are supported. Instruction read is initiated on the falling edge of /CS, and completed on the rising edge (8 clocks later). Write, Program, and Erase instructions must complete on a byte boundary (rising /CS), and most instructions are ignored when the BUSY bit of SR3 is set.

Dank: /* Registers */

2019-03-29T04:49:46Z

Registers

← Older revision		Revision as of 04:49, 29 March 2019
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	** MSB: Status register protect 0		** MSB: Status register protect 0
	** B6, B5, B4, B3: Block protection bits, all initialized to 1 (unless set via OTP)		** B6, B5, B4, B3: Block protection bits, all initialized to 1 (unless set via OTP)
	** B2: Type of protection ~~bit~~. When 1, protection applies to the lower end of the protected blocks; when 0, the upper end		** B2: TP (Type of protection). When 1, protection applies to the lower end of the protected blocks; when 0, the upper end
			*** When BP3 and either BP2 or BP1 are 1, TP is a don't care -- everything is protected
			*** When all BP bits are 0, TP is a don't care -- nothing is protected
	** B1: Write protection mode. Defaults to 0 (Software protection, Quad-SPI)		** B1: Write protection mode. Defaults to 0 (Software protection, Quad-SPI)
	*** Hardware write protection (/WP, /HOLD) cannot be used with Quad-SPI		*** Hardware write protection (/WP, /HOLD) cannot be used with Quad-SPI

Dank: /* Lines */

2019-03-29T04:46:46Z

Lines

← Older revision		Revision as of 04:46, 29 March 2019
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	** Transition to low places device into active mode		** Transition to low places device into active mode
	** /CS must track VCC during initialization and shutdown		** /CS must track VCC during initialization and shutdown
	* DI (IO0) data input / ~~data io0~~		* DI (IO0) data input / I/O-0
	* DO (IO1) data output / ~~data io1~~		** SPI must use this for writing. Dual- and Quad-SPI use it bidirectionally.
	* /WP (IO2) write protect input / ~~data io2~~		* DO (IO1) data output / I/O-1
	* /HOLD (IO3) hold input / ~~data io3~~		** SPI must use this for reading. Dual- and Quad-SPI use it bidirectionally.
			* /WP (IO2) write protect input / I/O-2
			** Used only in Hardware Protection mode (incompatible with Quad-SPI)
			* /HOLD (IO3) hold input / I/O-3
			** Used only in Hardware Protection mode (incompatible with Quad-SPI)
	* VCC power (2.7V--3.6V)		* VCC power (2.7V--3.6V)
	* GND		* GND
	~~/WP and /HOLD are only for SPI/Dual-SPI (Quad-SPI uses data io 0--3).~~ Data is ~~always~~ written on the rising edge of CLK, and read on the falling edge~~. SPI must write through DO and read through DI. Dual- and Quad-SPI treat data io pins as bidirectional~~.		Data is written on the rising edge of CLK, and read on the falling edge.

	===Registers===		===Registers===