SMP on x86

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** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).

** Pentium-M and Celerons usually lack SMT.

* Unduplicated resources are either split or shared between logical cores:

** Shared: reservation stations, data caches

** Split: reorder buffers, load/store buffers

** Duplicated: registers

* No programmable priority control exported, no implicit priorities defined

==Intel MP IDs==

* Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID

** The initial APIC ID can be retrieved via [[cpuid]], as can~~...~~

** The initial APIC ID can be retrieved via [[cpuid]], as can packaging data:

*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured

*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured

*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel

*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors

*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore

* APIC ID is formed of SMT_ID|CORE_ID|PACKAGE_ID, having widths defined by the packaging data:

** SMT_ID is 0 bits on a non-HyperThreaded processor.

** CORE_ID is 0 bits on a unicore package

** All remaining bits are devoted to PACKAGE_ID

==Interrupts==

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* "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network

[[Category: x86]]

[[CATEGORY: Hardware]]

SMP on x86: Difference between revisions

Dank (talk | contribs)

@@ Line 5: / Line 5: @@
 ** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).
 ** Pentium-M and Celerons usually lack SMT.
+* Unduplicated resources are either split or shared between logical cores:
+** Shared: reservation stations, data caches
+** Split: reorder buffers, load/store buffers
+** Duplicated: registers
+* No programmable priority control exported, no implicit priorities defined
 ==Intel MP IDs==
 * Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID
-** The initial APIC ID can be retrieved via [[cpuid]], as can...
+** The initial APIC ID can be retrieved via [[cpuid]], as can packaging data:
 *** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured
 *** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured
 *** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel
 *** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors
+*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore
+* APIC ID is formed of SMT_ID|CORE_ID|PACKAGE_ID, having widths defined by the packaging data:
+** SMT_ID is 0 bits on a non-HyperThreaded processor.
+** CORE_ID is 0 bits on a unicore package
+** All remaining bits are devoted to PACKAGE_ID
 ==Interrupts==
@@ Line 488: / Line 498: @@
 * "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network
 [[Category: x86]]
+[[CATEGORY: Hardware]]