Ivy Bridge: Difference between revisions
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A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL|OpenCL 1.1]] support. Ivy Bridge is expected to continue making use of the LGA1155 socket interface introduced with Sandy Bridge. | A 22nm update to [[Sandy Bridge]], scheduled for release in late 2012. This will be the first chip to feature Intel's new "FinFET" [http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29 trigate] nonplanar transistor technology. Its Panther Point chipset is expected to support [[PCIe|PCIe 3.0]], while the IGD will add DirectX 11 and [[OpenCL|OpenCL 1.1]] support. Ivy Bridge is expected to continue making use of the LGA1155 socket interface introduced with Sandy Bridge. | ||
==Architecture== | ==Architecture== | ||
[[File:Smep.jpeg|right|thumb|IDF 2011 slide on SMEP]] | |||
* The [[RDRAND]] instruction is made available on Ivy Bridge processors containing Bull Mountain hardware. | * The [[RDRAND]] instruction is made available on Ivy Bridge processors containing Bull Mountain hardware. | ||
* Supervisory Mode Execution Protection (SMEP) prohibits ring 0 code from executing memory writable by other rings | * Supervisory Mode Execution Protection (SMEP) prohibits ring 0 code from executing memory writable by other rings | ||
==Microarchitecture== | ==Microarchitecture== | ||
Microarchitecture is expected to be similar to that of [[Sandy Bridge]]. | Microarchitecture is expected to be similar to that of [[Sandy Bridge]]. | ||