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Intel's CPU release strategy. Approximately each year, either a "Tick" (new [[Architecture|microarchitecture]], for instance [[Nehalem]]) or a "Tock" (die shrink and incremental improvement of current microarchitecture, for instance [[Ivy Bridge]]) will be released. | Intel's CPU release strategy. Approximately each year, either a "Tick" (new [[Architecture|microarchitecture]], for instance [[Nehalem]]) or a "Tock" (die shrink and incremental improvement of current microarchitecture, for instance [[Ivy Bridge]]) will be released. | ||
{| class="wikitable" border="1" | |||
! Tick | |||
! Tock | |||
|- | |||
| [[Core]], 65nm (Q1 2006) | |||
| Penryn/Wolfdale/Dunnington, 45nm (Q4 2007) | |||
|- | |||
| [[Nehalem]], 45nm (Q4 2008) | |||
| Westmere, 32nm (Q1 2010) | |||
|- | |||
| [[Sandy Bridge]], 32nm (Q1 2011) | |||
| [[Ivy Bridge]], 22nm (sched. Q1 2012) | |||
|- | |||
| [[Haswell]], 22nm (sched. Q1 2013) | |||
| Broadwell, 14nm (sched. Q1 2014) | |||
|- | |||
|} | |||
[[CATEGORY: x86]] | [[CATEGORY: x86]] |
Latest revision as of 22:10, 11 December 2011
Intel's CPU release strategy. Approximately each year, either a "Tick" (new microarchitecture, for instance Nehalem) or a "Tock" (die shrink and incremental improvement of current microarchitecture, for instance Ivy Bridge) will be released.
Tick | Tock |
---|---|
Core, 65nm (Q1 2006) | Penryn/Wolfdale/Dunnington, 45nm (Q4 2007) |
Nehalem, 45nm (Q4 2008) | Westmere, 32nm (Q1 2010) |
Sandy Bridge, 32nm (Q1 2011) | Ivy Bridge, 22nm (sched. Q1 2012) |
Haswell, 22nm (sched. Q1 2013) | Broadwell, 14nm (sched. Q1 2014) |