Sandy Bridge

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[[File:Sandybridge.jpg|thumb|right|Sandy Bridge microarchitecture]]

[[File:Sandybridgedie.jpg|thumb|right|Sandy Bridge die]]

Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The P67, H67, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).

Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The "Cougar Point" line -- P67, H67, Z68, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).

==Architecture==

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** May be called from any processor state. Use the XSAVE/XRSTOR memory areas, specified by [[MSR|MSRs]].

* XMM [[SIMD|SSE]] registers map to the lower 128 bit of the corresponding YMM registers; the upper 128 bits will be zeroed out by SSE instructions.

** ~~Obviously,~~ YMM-oriented [[AVX]] and XMM-oriented [[SSE]] instructions ~~cannot~~ be freely mixed

** YMM-oriented [[AVX]] and XMM-oriented [[SSE]] instructions can be freely mixed

==Microarchitecture==

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Core i7 and Core i5 Sandy Bridge processors are thus far either quad- or dual-core, while Core i3 is strictly dual-core. Assuming [[HyperThreading|SMT]] to be enabled where possible, this means Core i7 provides 8 execution units, while Core i5 and Core i3 both provide 4. Without HyperThreading, the Core i3 provides 2, while the others provide 4. Currently, the Core i3 is limited to 3MB of cache, while Core i5/i7 support up to 8MB (current i5's ship with no more than 6MB).

===Release Sets===

* 2011-01-09 saw the first set of Sandy Bridge processors. TDP range: 45--96W. Freq range: 2.1GHz--3.4GHz, 3GHz--3.8GHz. Quad cores with 6--8MB LLC.

* 2011-01-09 saw the first set of Sandy Bridge processors.

** TDP range: 45--96W. Freq range: 2.1GHz--3.4GHz, 3GHz--3.8GHz. Quad cores with 6--8MB LLC.

** i7-2720QM, i5-2300, i5-2400, i5-2400S, i5-2500, i5-2500K, i5-2500S, i5-2500T, i7-2600, i7-2600K, i7-2600S, i7-2820QM, i7-2920XM, i7-2710QE, i7-2715QE

* 2011-02-20 sees a second set, with more mobile options (and the first Sandy Bridge Core i3's). TDP range: 17W--65W. Freq range: 1.4GHz--3.3GHz, 3--3.3GHz. Dual cores with 3--6MB LLC.

* 2011-02-20 sees a second set, with more mobile options (and the first Sandy Bridge Core i3's).

** TDP range: 17W--65W. Freq range: 1.4GHz--3.3GHz, 3--3.3GHz. Dual cores with 3--6MB LLC.

** i5-2540M, i5-2520M, i7-2620M, i3-2100, i3-2100T, i3-2120, i5-2390T, i5-2510E, i7-2629M, i7-2649M, i7-2657M, i7-2617M, i5-2537M, i5-2515E

K: unlocked S: performance-optimized T: power-optimized M: mobile QM: quad ~~mobile XM~~: eXtreme ~~mobile~~ E: ~~embedded QE: quad~~ embedded

''' K:''' unlocked '''S:''' performance-optimized '''T:''' power-optimized '''M:''' mobile '''Q:''' quad '''X:''' eXtreme '''E:''' embedded

==Processor Support==

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GMA HD2 improves transcendental math hardware over HD1, and expands the register file. The 2000-series IGP has 6 execution units, while the 3000 has 12. Currently, 3000-series IGP's are reserved for K-series processors (the P67 performance-oriented chipset cannot make use of the IGP, and requires a discrete graphics adapter). The IGP has limited locking on its clock -- the H67 chipset can control IGP multipliers.

Unlike [[Larrabee]]'s fully programmable shaders (suitable for [[GPGPU]]), Sandy Bridge IGP ~~makes extensive use of~~ fixed-function components. The instruction set is said to closely parallel the DirectX 10 API. There are a fixed 120 registers per thread, as opposed to the dynamically partitionable register file of previous Intel HD Graphics.

Unlike [[Larrabee]]'s fully programmable shaders (suitable for [[GPGPU]]), Sandy Bridge IGP devotes significant space to fixed-function components. The instruction set is said to closely parallel the DirectX 10 API. There are a fixed 120 registers per thread, as opposed to the dynamically partitionable register file of previous Intel HD Graphics. Intel HD is a valid [[OpenCL]] target.

The IGP runs on its own voltage and frequency planes, and supports its own [[Turbo Boost]]. It supports [[HDMI]] 1.4.

===MFX===

<blockquote>Two key versions of graphics will be available, Intel® HD Graphics 2000 and Intel® HD Graphics 3000/3000+, with Intel® HD Graphics 2000 targeting lower voltage (lower power) applications and Intel® HD Graphics 3000 a more mainstream set of applications. -- [http://software.intel.com/en-us/articles/intel-graphics-developers-guides/ Intel Graphics Developer Guide]</blockquote>

====Intel HD Graphics====

[[File:intelhdarch.png|right|thumb|Intel HD architecture]]

At the heart of Intel HD is an array of "Execution Units", unified SMT SIMD shaders with unified transcendental units. Fixed-function hardware covers clipping and setup/early-z, as well as decoding of vertex, pixel and geometry shaders (these last are fed by the "Command Streamer", which also feeds video processing, the 2d unit, and display hardware).

====MFX====

The Multi-Format Codec (MFX) engine is fixed functionality for high-performance, low-power transcoding. It features intensely parallel hardware.

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** The Intel H67 Express Chipset Platform Block Diagram does claim that GMA-HD will not be available on all processors

** ...but none are currently planned for release.

* The Z68 chipset, scheduled for release in Q2 2011, addresses these issues

==Sources==

* "[http://www.realworldtech.com/page.cfm?ArticleID=RWT080811195102 Intel's Sandy Bridge Graphics Architecture]", Real World Technologies, 2011-08-08

* "[http://techreport.com/articles.x/20190 Introducing the P67 Express]", The Tech Report, 2011-01-04 (Geoff Gasior)

* "[http://www.pcper.com/article.php?aid=1057 Intel Core i7-2600K (and friends) Sandy Bridge Processor Review]", PC Perspective, 2011-01-02 (Ryan Shrout)

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* "[http://ark.intel.com/MySearch.aspx?TBT=true&CodeNameText=Sandy%20Bridge Sandy Bridge Products]" at http://www.intel.com

* "[http://www.realworldtech.com/page.cfm?ArticleID=RWT091810191937 Intel's Sandy Bridge Microarchitecture]" at Real World Technologies, 2010-09-25 (David Kanter)

* "[http://software.intel.com/en-us/articles/intel-graphics-developers-guides/ Intel Graphics Developer Guide]", 321671-005US, 2011-01

[[CATEGORY: x86]]

[[CATEGORY: Hardware]]

Sandy Bridge: Difference between revisions

Dank (talk | contribs)

@@ Line 1: / Line 1: @@
 [[File:Sandybridge.jpg|thumb|right|Sandy Bridge microarchitecture]]
 [[File:Sandybridgedie.jpg|thumb|right|Sandy Bridge die]]
-Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The P67, H67, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).
+Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The "Cougar Point" line -- P67, H67, Z68, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).
 ==Architecture==
@@ Line 9: / Line 9: @@
 ** May be called from any processor state. Use the XSAVE/XRSTOR memory areas, specified by [[MSR|MSRs]].
 * XMM [[SIMD|SSE]] registers map to the lower 128 bit of the corresponding YMM registers; the upper 128 bits will be zeroed out by SSE instructions.
-** Obviously, YMM-oriented [[AVX]] and XMM-oriented [[SSE]] instructions cannot be freely mixed
+** YMM-oriented [[AVX]] and XMM-oriented [[SSE]] instructions can be freely mixed
 ==Microarchitecture==
@@ Line 69: / Line 69: @@
 Core i7 and Core i5 Sandy Bridge processors are thus far either quad- or dual-core, while Core i3 is strictly dual-core. Assuming [[HyperThreading|SMT]] to be enabled where possible, this means Core i7 provides 8 execution units, while Core i5 and Core i3 both provide 4. Without HyperThreading, the Core i3 provides 2, while the others provide 4. Currently, the Core i3 is limited to 3MB of cache, while Core i5/i7 support up to 8MB (current i5's ship with no more than 6MB).
 ===Release Sets===
-* 2011-01-09 saw the first set of Sandy Bridge processors. TDP range: 45--96W. Freq range: 2.1GHz--3.4GHz, 3GHz--3.8GHz. Quad cores with 6--8MB LLC.
+* 2011-01-09 saw the first set of Sandy Bridge processors.
+** TDP range: 45--96W. Freq range: 2.1GHz--3.4GHz, 3GHz--3.8GHz. Quad cores with 6--8MB LLC.
 ** i7-2720QM, i5-2300, i5-2400, i5-2400S, i5-2500, i5-2500K, i5-2500S, i5-2500T, i7-2600, i7-2600K, i7-2600S, i7-2820QM, i7-2920XM, i7-2710QE, i7-2715QE
-* 2011-02-20 sees a second set, with more mobile options (and the first Sandy Bridge Core i3's). TDP range: 17W--65W. Freq range: 1.4GHz--3.3GHz, 3--3.3GHz. Dual cores with 3--6MB LLC.
+* 2011-02-20 sees a second set, with more mobile options (and the first Sandy Bridge Core i3's).
+** TDP range: 17W--65W. Freq range: 1.4GHz--3.3GHz, 3--3.3GHz. Dual cores with 3--6MB LLC.
 ** i5-2540M, i5-2520M, i7-2620M, i3-2100, i3-2100T, i3-2120, i5-2390T, i5-2510E, i7-2629M, i7-2649M, i7-2657M, i7-2617M, i5-2537M, i5-2515E
-K: unlocked S: performance-optimized T: power-optimized M: mobile QM: quad mobile XM: eXtreme mobile E: embedded QE: quad embedded
+''' K:''' unlocked '''S:''' performance-optimized '''T:''' power-optimized '''M:''' mobile '''Q:''' quad '''X:''' eXtreme '''E:''' embedded
 ==Processor Support==
@@ Line 86: / Line 88: @@
 GMA HD2 improves transcendental math hardware over HD1, and expands the register file. The 2000-series IGP has 6 execution units, while the 3000 has 12. Currently, 3000-series IGP's are reserved for K-series processors (the P67 performance-oriented chipset cannot make use of the IGP, and requires a discrete graphics adapter). The IGP has limited locking on its clock -- the H67 chipset can control IGP multipliers.
-Unlike [[Larrabee]]'s fully programmable shaders (suitable for [[GPGPU]]), Sandy Bridge IGP makes extensive use of fixed-function components. The instruction set is said to closely parallel the DirectX 10 API. There are a fixed 120 registers per thread, as opposed to the dynamically partitionable register file of previous Intel HD Graphics.
+Unlike [[Larrabee]]'s fully programmable shaders (suitable for [[GPGPU]]), Sandy Bridge IGP devotes significant space to fixed-function components. The instruction set is said to closely parallel the DirectX 10 API. There are a fixed 120 registers per thread, as opposed to the dynamically partitionable register file of previous Intel HD Graphics. Intel HD is a valid [[OpenCL]] target.
 The IGP runs on its own voltage and frequency planes, and supports its own [[Turbo Boost]]. It supports [[HDMI]] 1.4.
-===MFX===
+<blockquote>Two key versions of graphics will be available, Intel® HD Graphics 2000 and Intel® HD Graphics 3000/3000+, with Intel® HD Graphics 2000 targeting lower voltage (lower power) applications and Intel® HD Graphics 3000 a more mainstream set of applications. -- [http://software.intel.com/en-us/articles/intel-graphics-developers-guides/ Intel Graphics Developer Guide]</blockquote>
+====Intel HD Graphics====
+[[File:intelhdarch.png|right|thumb|Intel HD architecture]]
+At the heart of Intel HD is an array of "Execution Units", unified SMT SIMD shaders with unified transcendental units. Fixed-function hardware covers clipping and setup/early-z, as well as decoding of vertex, pixel and geometry shaders (these last are fed by the "Command Streamer", which also feeds video processing, the 2d unit, and display hardware).
+====MFX====
 The Multi-Format Codec (MFX) engine is fixed functionality for high-performance, low-power transcoding. It features intensely parallel hardware.
@@ Line 101: / Line 108: @@
 ** The Intel H67 Express Chipset Platform Block Diagram does claim that GMA-HD will not be available on all processors
 ** ...but none are currently planned for release.
+* The Z68 chipset, scheduled for release in Q2 2011, addresses these issues
 ==Sources==
+* "[http://www.realworldtech.com/page.cfm?ArticleID=RWT080811195102 Intel's Sandy Bridge Graphics Architecture]", Real World Technologies, 2011-08-08
 * "[http://techreport.com/articles.x/20190 Introducing the P67 Express]", The Tech Report, 2011-01-04 (Geoff Gasior)
 * "[http://www.pcper.com/article.php?aid=1057 Intel Core i7-2600K (and friends) Sandy Bridge Processor Review]", PC Perspective, 2011-01-02 (Ryan Shrout)
@@ Line 109: / Line 118: @@
 * "[http://ark.intel.com/MySearch.aspx?TBT=true&CodeNameText=Sandy%20Bridge Sandy Bridge Products]" at http://www.intel.com
 * "[http://www.realworldtech.com/page.cfm?ArticleID=RWT091810191937 Intel's Sandy Bridge Microarchitecture]" at Real World Technologies, 2010-09-25 (David Kanter)
+* "[http://software.intel.com/en-us/articles/intel-graphics-developers-guides/ Intel Graphics Developer Guide]", 321671-005US, 2011-01
 [[CATEGORY: x86]]
 [[CATEGORY: Hardware]]