Sandy Bridge

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[[File:Sandybridge.jpg|thumb|right|Sandy Bridge microarchitecture]]

[[File:Sandybridgedie.jpg|thumb|right|Sandy Bridge die]]

Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The P67, H67, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).

Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The "Cougar Point" line -- P67, H67, Z68, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).

==Architecture==

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** The Intel H67 Express Chipset Platform Block Diagram does claim that GMA-HD will not be available on all processors

** ...but none are currently planned for release.

* The Z68 chipset, scheduled for release in Q2 2011, addresses these issues

==Sources==

* "[http://www.realworldtech.com/page.cfm?ArticleID=RWT080811195102 Intel's Sandy Bridge Graphics Architecture]", Real World Technologies, 2011-08-08

* "[http://techreport.com/articles.x/20190 Introducing the P67 Express]", The Tech Report, 2011-01-04 (Geoff Gasior)

* "[http://www.pcper.com/article.php?aid=1057 Intel Core i7-2600K (and friends) Sandy Bridge Processor Review]", PC Perspective, 2011-01-02 (Ryan Shrout)

Sandy Bridge: Difference between revisions

Dank (talk | contribs)

@@ Line 1: / Line 1: @@
 [[File:Sandybridge.jpg|thumb|right|Sandy Bridge microarchitecture]]
 [[File:Sandybridgedie.jpg|thumb|right|Sandy Bridge die]]
-Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The P67, H67, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).
+Intel released Sandy Bridge in January 2011 as a major revision of [[Nehalem]]. Core i7 and i5 models were released simultaneously; a 2011-02 drop will include i3's. All released and planned Sandy Bridge packages support on-die integrated [http://en.wikipedia.org/wiki/Intel_GMA GMA-HD2] graphics processors and make use of the new [http://en.wikipedia.org/wiki/LGA_1155 LGA 1155] ("H2") socket, a successor to [http://en.wikipedia.org/wiki/LGA_1156 LGA 1156] ("Socket H"). The "Cougar Point" line -- P67, H67, Z68, Q67 and B65 chipsets ("Platform Controller Hub" or PCH in recent Intel terminology) have been released to support Sandy Bridge, and are compatible with all current variants. It uses the scalable ring-based bus designed for [[Larrabee]] (introduced on [[Nehalem|Nehalem EX]]) and supports [[AVX]] and [[AES-NI]] instructions. Sandy Bridge processors (and their on-die IGPs) use a 32nm process ([[Ivy Bridge]], a planned minor successor to Sandy Bridge, will use 22nm process).
 ==Architecture==
@@ Line 108: / Line 108: @@
 ** The Intel H67 Express Chipset Platform Block Diagram does claim that GMA-HD will not be available on all processors
 ** ...but none are currently planned for release.
+* The Z68 chipset, scheduled for release in Q2 2011, addresses these issues
 ==Sources==
+* "[http://www.realworldtech.com/page.cfm?ArticleID=RWT080811195102 Intel's Sandy Bridge Graphics Architecture]", Real World Technologies, 2011-08-08
 * "[http://techreport.com/articles.x/20190 Introducing the P67 Express]", The Tech Report, 2011-01-04 (Geoff Gasior)
 * "[http://www.pcper.com/article.php?aid=1057 Intel Core i7-2600K (and friends) Sandy Bridge Processor Review]", PC Perspective, 2011-01-02 (Ryan Shrout)