SIMD: Difference between revisions
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First introduced on the Illiac IV, and not to be confused with vector processing. | [[File:Simd.jpeg|thumb|right|A 4-way SIMD unit]] | ||
First introduced on the Illiac IV, and not to be confused with vector processing. SIMD-capable units are often taxonomized via <tt>SIMDnXm</tt> nomenclature, where '''n''' is the issue width and '''m''' is the channel width; a superscalar processor would be SIMDnX1, while a scalar SISD processor would be SIMD1X1. | |||
==Compilers and Assemblers== | ==Compilers and Assemblers== | ||
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==Data Types (taken from SSE specs)== | ==Data Types (taken from SSE specs)== | ||
These do not necessarily map to | These do not necessarily map to [[C]] data types of the same name, for any given compiler! | ||
* '''half precision''': 16-bit IEEE 754 floating-point (bias-15) (IEEE 754 2008 '''binary16''') | * '''half precision''': 16-bit IEEE 754 floating-point (bias-15) (IEEE 754 2008 '''binary16''') | ||
* '''single''': 32-bit IEEE 754 floating-point (bias-127) (IEEE 754 2008 '''binary32''') | * '''single''': 32-bit IEEE 754 floating-point (bias-127) (IEEE 754 2008 '''binary32''') | ||
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* '''word''': 32-bit two's complement integer | * '''word''': 32-bit two's complement integer | ||
* '''doubleword''', '''dword''': 64-bit two's complement integer | * '''doubleword''', '''dword''': 64-bit two's complement integer | ||
==x86 YMM== | ==x86 YMM== | ||
The [http://software.intel.com/en-us/avx/ AVX] (Advanced Vector eXtensions) were introduced on Intel's [[Sandy Bridge]] (2010) and AMD's [[Bulldozer]] (2011). They operate on the 256-bit YMM registers (YMM0..YMM15), which are aliased by the [[SIMD#x86_XMM|XMM]] registers. They are encoded using the [[VEX]] scheme. Support for AVX can be determined via: | The [http://software.intel.com/en-us/avx/ AVX] (Advanced Vector eXtensions) were introduced on Intel's [[Sandy Bridge]] (2010) and AMD's [[Bulldozer]] (2011). They operate on the 256-bit YMM registers (YMM0..YMM15), which are aliased by the [[SIMD#x86_XMM|XMM]] registers. They are encoded using the [[VEX]] scheme. Support for AVX can be determined via: | ||
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* Issue XGETBV and verify that XFEATURE_ENABLED_MASK[2:1] = 0x3 (XMM state and YMM state are enabled by OS) | * Issue XGETBV and verify that XFEATURE_ENABLED_MASK[2:1] = 0x3 (XMM state and YMM state are enabled by OS) | ||
* Determine that [[CPUID]].1:ECX.AVX[bit 28] is set (AVX instructions supported) | * Determine that [[CPUID]].1:ECX.AVX[bit 28] is set (AVX instructions supported) | ||
==x86 AVX== | |||
New 256-bit YMM registers. | |||
===New [[Haswell]] Instructions=== | |||
* AVX2 instructions: integer SIMD using AVX's 256-bit YMM registers. | |||
* YMM-SIMD bit manipulation, permute, gather, shift, and FMA | |||
===AVX1=== | |||
* Introduced on [[Sandy Bridge]] | |||
==x86 XMM== | ==x86 XMM== | ||
The Streaming SIMD Extensions operate on the 128-bit XMM registers (XMM0..XMM7 in 32-bit mode, XMM0..XMM15 in 64-bit mode). In its original incarnation on the PIII, execution units (but not registers) were shared with the x87 floating-point architecture. The execution units were separated in the NetBurst microarchitecture. In the Core microarchitecture, the execution engine has been widened for greater SSE throughput. | The Streaming SIMD Extensions operate on the 128-bit XMM registers (XMM0..XMM7 in 32-bit mode, XMM0..XMM15 in 64-bit mode). In its original incarnation on the PIII, execution units (but not registers) were shared with the x87 floating-point architecture. The execution units were separated in the NetBurst microarchitecture. In the Core microarchitecture, the execution engine has been widened for greater SSE throughput. | ||
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*Originally known as Prescott New Instructions, and introduced on P4-Prescott | *Originally known as Prescott New Instructions, and introduced on P4-Prescott | ||
*<tt>[http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedProjects/instructions/instruct32_hh/movddup--move_one_double-fp_and_duplicate.htm movddup]</tt> -- move a double from a 8-byte-aligned memory location or lower half of XMM register to upper half, then duplicate upper half to lower half | *<tt>[http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedProjects/instructions/instruct32_hh/movddup--move_one_double-fp_and_duplicate.htm movddup]</tt> -- move a double from a 8-byte-aligned memory location or lower half of XMM register to upper half, then duplicate upper half to lower half | ||
*<tt>MWAIT/MONITOR</tt> | |||
====SSSE3 (TNI/MNI)==== | ====SSSE3 (TNI/MNI)==== | ||
*Introduced with the Core microarchitecture. Sometimes referred to as Tejas New Instructions or Merom New Instructions | *Introduced with the Core microarchitecture. Sometimes referred to as Tejas New Instructions or Merom New Instructions | ||
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* The [http://en.wikipedia.org/wiki/FMA_instruction_set FMA instruction set] extension to x86 should hit around 2011, providing floating-point fused multiply-add | * The [http://en.wikipedia.org/wiki/FMA_instruction_set FMA instruction set] extension to x86 should hit around 2011, providing floating-point fused multiply-add | ||
** AMD appears to call this [http://en.wikipedia.org/wiki/FMA_instruction_set FMA4], part of what was SSE5 | ** AMD appears to call this [http://en.wikipedia.org/wiki/FMA_instruction_set FMA4], part of what was SSE5 | ||
==x87 MMX== | ==x87 MMX== | ||
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* AMD64 Architecture Programmer’s Manual Volume 6: [http://support.amd.com/us/Processor_TechDocs/43479.pdf 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions] | * AMD64 Architecture Programmer’s Manual Volume 6: [http://support.amd.com/us/Processor_TechDocs/43479.pdf 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions] | ||
* Agner Fog's [http://www.agner.org/optimize/instruction_tables.pdf x86 Instruction Tables] | * Agner Fog's [http://www.agner.org/optimize/instruction_tables.pdf x86 Instruction Tables] | ||
* "[http://software.intel.com/en-us/blogs/2011/06/13/haswell-new-instruction-descriptions-now-available Haswell New Instruction Descriptions now Available]", Intel Software Developer Network, 2011-06-13 | |||
* General [[architecture]] page | * General [[architecture]] page | ||
[[Category: x86]] | [[Category: x86]] | ||