Winbond

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===[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]===

A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected ~~bits~~ are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).

A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bytes are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).

The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.

The device has JEDEC Manufacturer ID 0xEF and ~~evice~~ ID 0xAA21.

The device has JEDEC Manufacturer ID 0xEF and Device ID 0xAA21.

Bad blocks are marked at the factory with a non-0xff byte as their first byte, and a non-0xff byte as the first byte of the first page's Spare Area (i.e. all blocks marked with 0xff as their first byte, and as the first byte of the first page's Spare Area, are considered good). Before executing the first program or erase instruction, pages ought be inspected, and added to the LUT if necessary.

Winbond: Difference between revisions

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 ===[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]===
-A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).
+A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bytes are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte. The device also provides a 20-entry LUT for mapping logical page addresses away to undamaged physical page addresses (the manufacturer might set some of these entries at the factory).
 The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.
-The device has JEDEC Manufacturer ID 0xEF and evice ID 0xAA21.
+The device has JEDEC Manufacturer ID 0xEF and Device ID 0xAA21.
 Bad blocks are marked at the factory with a non-0xff byte as their first byte, and a non-0xff byte as the first byte of the first page's Spare Area (i.e. all blocks marked with 0xff as their first byte, and as the first byte of the first page's Spare Area, are considered good). Before executing the first program or erase instruction, pages ought be inspected, and added to the LUT if necessary.