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nvidia 0000:07:00.0: setting latency timer to 64
nvidia 0000:07:00.0: setting latency timer to 64
NVRM: loading NVIDIA UNIX x86_64 Kernel Module  190.53  Wed Dec  9 15:29:46 PST 2009</pre>
NVRM: loading NVIDIA UNIX x86_64 Kernel Module  190.53  Wed Dec  9 15:29:46 PST 2009</pre>
Once the module is loaded, CUDA should be able to find the device. See [[CUDA#deviceQuery_Output|below]] for sample outputs. Each device has a '''compute capability''', though this does not encompass all differentiated capabilities (see also <tt>deviceOverlap</tt> and <tt>canMapHostMemory</tt>...). Note that "emulation mode" has been removed as of CUDA Toolkit Version 3.1.
Once the module is loaded, CUDA should be able to find the device. See [[CUDA#deviceQuery_Output|below]] for sample outputs. Each device has a [[CUDA#Compute_Capabilities|compute capability]], though this does not encompass all differentiated capabilities (see also <tt>deviceOverlap</tt> and <tt>canMapHostMemory</tt>...). Note that "emulation mode" has been removed as of CUDA Toolkit Version 3.1.


==CUDA model==
==CUDA model==
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===Streaming Multiprocessor===
===Streaming Multiprocessor===
* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor|Stream Processors]] (SPs).
* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor|Stream Processors]] (SPs).
** 8192 registers for compute capability <= 1.1, otherwise
** 8K registers for compute capability <= 1.1, otherwise
** 16384 for compute capability <= 1.3
** 16K for compute capability <= 1.3, otherwise
** 32K for compute capability <= 2.1, otherwise
** 64K through at least compute capability 3.5
* A group of threads which share a memory and can "synchronize their execution to coördinate accesses to memory" (use a [[barrier]]) form a '''block'''. Each thread has a ''threadId'' within its (three-dimensional) block.
* A group of threads which share a memory and can "synchronize their execution to coördinate accesses to memory" (use a [[barrier]]) form a '''block'''. Each thread has a ''threadId'' within its (three-dimensional) block.
** For a block of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>, D<sub>z</sub>&gt;, the threadId of the thread having index &lt;x, y, z&gt; is (x + y * D<sub>x</sub> + z * D<sub>y</sub> * D<sub>x</sub>).
** For a block of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>, D<sub>z</sub>&gt;, the threadId of the thread having index &lt;x, y, z&gt; is (x + y * D<sub>x</sub> + z * D<sub>y</sub> * D<sub>x</sub>).
* Register allocation is performed per-block, and rounded up to the nearest
* Register allocation is performed per-block, and rounded up to the nearest
** 256 registers per block for compute capability <= 1.1, otherwise
** 256 registers per block for compute capability <= 1.1, otherwise
** 512 registers per block for compute capability <= 1.3.
** 512 registers per block for compute capability <= 1.3
* A group of blocks which share a kernel form a '''grid'''. Each block (and each thread within that block) has a ''blockId'' within its (two-dimensional) grid.
* A group of blocks which share a kernel form a '''grid'''. Each block (and each thread within that block) has a ''blockId'' within its (two-dimensional) grid.
** For a grid of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>&gt;, the blockId of the block having index &lt;x, y&gt; is (x + y * D<sub>x</sub>).
** For a grid of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>&gt;, the blockId of the block having index &lt;x, y&gt; is (x + y * D<sub>x</sub>).
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===Compute Capabilities===
===Compute Capabilities===
The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been backwards-compatible.
The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been fowards-compatible, though recent CUDA toolkits will not generate code for CC1 or 2.
 
{| border="1" class="wikitable"
{| border="1" class="wikitable"
! Resource
! Resource
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! 2.1 SM
! 2.1 SM
! 3.0 SMX
! 3.0 SMX
! 3.5 SMX
! 7.0 SM
! 7.5 SM
|-
|-
|CUDA cores
|CUDA cores
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|48
|48
|192
|192
|192
|64/32<br/>64/8
|64/2<br/>64/8
|-
|-
|Warp schedulers
|Schedulers
|1
|1
|1
|1
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|2
|2
|2
|2
|4
|4
|4
|4
|4
|-
|-
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|2
|2
|2
|2
|2
|1
|1
|-
|-
|Threads
|Threads
|768
|768
|768
|768
|1024
|1K
|1024
|1K
|1536
|1536
|1536
|1536
|2048
|2K
|2K
|2K
|1K
|-
|-
|Warps
|Warps
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|48
|48
|64
|64
|64
|64
|32
|-
|-
|Blocks
|Blocks
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|8
|8
|16
|16
|16
|32
|16
|-
|32-bit regs
|8K
|8K
|16K
|16K
|32K
|32K
|64K
|64K
|64K
|64K
|-
|-
|32-bit registers
|Examples
|8192
|G80
|8192
|G9x
|16384
|GT21x
|16384
|GT200
|32768
|GF110
|32768
|GF10x
|65536
|GK104
|GK110
|GV100
|TU10x
|-
|-
}
|}
{| border="1"
{| border="1"
! Revision
! Revision
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* 32 SFUs per SMX, 32 TFUs per ROP
* 32 SFUs per SMX, 32 TFUs per ROP
* 4 warp schedulers per SMX, capable of issuing two instructions per clock
* 4 warp schedulers per SMX, capable of issuing two instructions per clock
* Double-precision instructions can be paired with non-DP
** Previously, double-precision instructions couldn't be paired with anything
* ''PTX 3.0''
* ''PTX 3.0''
** <tt>madc</tt> and <tt>mad.cc</tt> instructions
** <tt>madc</tt> and <tt>mad.cc</tt> instructions
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** DWARF debugging symbols support
** DWARF debugging symbols support


|-
| 3.5
|
* 255 registers per thread
* "CUDA Dynamic Parallelism", the ability to spawn threads from within device code
* ''PTX 3.1''
** A funnel shift instruction, <tt>shf</tt>
** Loading read-only global data through the non-coherent texture cache, <tt>ld.global.nc</tt>
** 64-bit atomic/reduction operators extended to {or, xor, and, integer min, integer max}
** Mipmap type support
** Indirect texture/surface support
** Extends generic addressing to include the const state space
|-
| 7.0
|
* ''PTX 6.3''
* Tensor cores
* Independent thread scheduling
|-
| 7.5
|
* ''PTX 6.4''
* Integer matrix multiplication in tensor cores
|-
|-
|}
|}
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* <tt>-X -v</tt> displays per-thread register usage
* <tt>-X -v</tt> displays per-thread register usage
* <tt>-X -abi=no</tt> disables the PTX ABI, saving registers but taking away your stack
* <tt>-X -abi=no</tt> disables the PTX ABI, saving registers but taking away your stack
* <tt>-dlcm={cg,cs,ca} modifies cache behavior for loads
* <tt>-dlcm={cg,cs,ca}</tt> modifies cache behavior for loads
* <tt>-dscm={cw,cs} modifies cache behavior for stores
* <tt>-dscm={cw,cs}</tt> modifies cache behavior for stores
===SDK's common.mk===
===SDK's common.mk===
This assumes use of the SDK's common.mk, as recommended by the documentation.
This assumes use of the SDK's common.mk, as recommended by the documentation.
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* A run time limit is activated by default if the device is being used to drive a display.
* A run time limit is activated by default if the device is being used to drive a display.
* Please feel free to [mailto:nickblack@acm.org send me output!]
* Please feel free to [mailto:nickblack@acm.org send me output!]
{| border="1"
{| border="1"
! Device name
! Device name
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! MP's
! MP's
! Cores
! Cores
! Const mem
! Shmem/block
! Shmem/block
! Reg/block
! Reg/block
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! Shared maps?
! Shared maps?
|-
|-
! COLSPAN="15" style="background:#8070D8;" | Compute capability 3.0
! COLSPAN="13" style="background:#eebeb6;" | Compute capability 7.0
|-
| Tesla V100
| 16GB
| 84
| 5376/2688/672
|
|
|
|
|
| 1.53GHz
| Yes
| No
| Yes
|-
! COLSPAN="13" style="background:#8070D8;" | Compute capability 3.0
|-
|-
| GeForce GTX 680
| GeForce GTX 680
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| 1536
| 1536
|  
|  
|
|
|
|
|
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| Yes
| Yes
|-
|-
! COLSPAN="15" style="background:#ffdead;" | Compute capability 2.1
! COLSPAN="13" style="background:#ffdead;" | Compute capability 2.1
|-
|-
| GeForce GTX 560 Ti
| GeForce GTX 560 Ti
|
|
|
|
|
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|-
|-
| GeForce GTX 550 Ti
| GeForce GTX 550 Ti
|
|
|
|
|
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| 7
| 7
| 224
| 224
| 64k
| 48k
| 48k
| 32k
| 32k
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|-
|-
| GeForce GTS 450
| GeForce GTS 450
|
|
|
|
|
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|
|
|-
|-
! COLSPAN="15" style="background:#ffdead;" | Compute capability 2.0
! COLSPAN="13" style="background:#ffdead;" | Compute capability 2.0
|-
|-
| GeForce GTX 580
| GeForce GTX 580
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| 16
| 16
| 512
| 512
|
|
|
|
|
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| 14
| 14
| 448
| 448
| 64k
| 48k
| 48k
| 32k
| 32k
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| 14
| 14
| 448
| 448
| 64k
| 48k
| 48k
| 32k
| 32k
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| 15
| 15
| 480
| 480
|
|  
|  
|  
|  
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| 14
| 14
| 448
| 448
|
|  
|  
|  
|  
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|
|
|-
|-
! COLSPAN="15" style="background:#efefef;" | Compute capability 1.3
! COLSPAN="13" style="background:#efefef;" | Compute capability 1.3
|-
|-
| Tesla C1060
| Tesla C1060
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| 30
| 30
| 240
| 240
| 65536b
| 16384b
| 16384b
| 16384
| 16384
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| 30
| 30
| 240
| 240
| 65536b
| 16384b
| 16384b
| 16384
| 16384
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| 30
| 30
| 240
| 240
| 65536b
| 16384b
| 16384b
| 16384
| 16384
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| 30
| 30
| 240
| 240
| 65536b
| 16384b
| 16384b
| 16384
| 16384
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| 27
| 27
| 216
| 216
| 65536b
| 16384b
| 16384b
| 16384
| 16384
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| Yes
| Yes
|-
|-
! COLSPAN="15" style="background:#efefef;" | Compute capability 1.2
! COLSPAN="13" style="background:#efefef;" | Compute capability 1.2
|-
|-
| GeForce GT 360M
| GeForce GT 360M
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| 12
| 12
| 96
| 96
| 65536b
| 16384b
| 16384b
| 16384
| 16384
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| 2
| 2
| 16
| 16
| 65536b
| 16384b
| 16384b
| 16384
| 16384
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| 12
| 12
| 96
| 96
| 65536b
| 16384b
| 16384b
| 16384
| 16384
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| Yes
| Yes
|-
|-
! COLSPAN="15" style="background:#efefef;" | Compute capability 1.1
! COLSPAN="13" style="background:#efefef;" | Compute capability 1.1
|-
|-
| ION
| ION
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| 2
| 2
| 16
| 16
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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| 2
| 2
| 16
| 16
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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| 16
| 16
| 128
| 128
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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| 16
| 16
| 128
| 128
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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| 8
| 8
| 64
| 64
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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| 2
| 2
| 16
| 16
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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| 16
| 16
| 128
| 128
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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| 4
| 4
| 32
| 32
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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| 1
| 1
| 8
| 8
| 65536b
| 16384b
| 16384b
| 8192
| 8192
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