SIMD: Difference between revisions

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First introduced on the Illiac IV, and not to be confused with vector processing.

[[File:Simd.jpeg|thumb|right|A 4-way SIMD unit]]

First introduced on the Illiac IV, and not to be confused with vector processing. SIMD-capable units are often taxonomized via <tt>SIMDnXm</tt> nomenclature, where '''n''' is the issue width and '''m''' is the channel width; a superscalar processor would be SIMDnX1, while a scalar SISD processor would be SIMD1X1.

==Compilers and Assemblers==

* [[GCC]] can issue SIMD four different ways:

** [http://gcc.gnu.org/onlinedocs/gcc/Submodel-Options.html#Submodel-Options Target-specific code generation] will sometimes use scalar SIMD

** [http://gcc.gnu.org/onlinedocs/gcc/Target-Builtins.html Target-specific builtins], using [http://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html vector extensions]

** [[GCC#Inline_Assembly|Inline assembly]], using syntax of the [http://sourceware.org/binutils/docs/as/index.html GNU Assembler] and a baroque register specification convention

** [http://gcc.gnu.org/projects/tree-ssa/vectorization.html Auto-vectorization] from [[GCC|gcc's]] <tt>autovect</tt> branch attempts to autovectorize some loops

==Data Types (taken from SSE specs)==

These do not necessarily map to ~~the~~ C data types of the same name, for any given compiler!

These do not necessarily map to [[C]] data types of the same name, for any given compiler!

* '''half precision''': 16-bit IEEE 754 floating-point (bias-15) (IEEE 754 2008 '''binary16''')

* '''single''': 32-bit IEEE 754 floating-point (bias-127) (IEEE 754 2008 '''binary32''')

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* '''doubleword''', '''dword''': 64-bit two's complement integer

==x86 YMM==

The [http://software.intel.com/en-us/avx/ AVX] (Advanced Vector eXtensions) were introduced on Intel's [[Sandy Bridge]] (2010) and AMD's [[Bulldozer]] (2011). They operate on the 256-bit YMM registers (YMM0..YMM15), which are aliased by the [[SIMD#x86_XMM|XMM]] registers. They are encoded using the [[VEX]] scheme. Support for AVX can be determined via:

* Determine that [[CPUID]].1:ECX.OSXSAVE[bit 27] is set (XGETBV is enabled for application use)

* Issue XGETBV and verify that XFEATURE_ENABLED_MASK[2:1] = 0x3 (XMM state and YMM state are enabled by OS)

* Determine that [[CPUID]].1:ECX.AVX[bit 28] is set (AVX instructions supported)

==x86 AVX==

New 256-bit YMM registers.

===New [[Haswell]] Instructions===

* AVX2 instructions: integer SIMD using AVX's 256-bit YMM registers.

* YMM-SIMD bit manipulation, permute, gather, shift, and FMA

===AVX1===

* Introduced on [[Sandy Bridge]]

==x86 XMM==

The Streaming SIMD Extensions operate on the 128-bit XMM registers (XMM0..XMM7 in 32-bit mode, XMM0..XMM15 in 64-bit mode).

The Streaming SIMD Extensions operate on the 128-bit XMM registers (XMM0..XMM7 in 32-bit mode, XMM0..XMM15 in 64-bit mode). In its original incarnation on the PIII, execution units (but not registers) were shared with the x87 floating-point architecture. The execution units were separated in the NetBurst microarchitecture. In the Core microarchitecture, the execution engine has been widened for greater SSE throughput.

===SSE5 (AMD)===

* Unimplemented extensions competing with SSE4, encoded using a method incompatible with VEX

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===SSE4 (Intel)===

~~====SSE4a====~~

====SSE4.1====

[[File:Dppd.gif|thumb|DPPD instruction dataflow]]

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====SSE4.2====

[[File:Intel Nehalem arch.png|thumb|Intel Nehalem microarchitecture]]

[[File:Intel Nehalem arch.png|thumb|Intel [[Nehalem]] microarchitecture]]

*Introduced on Nehalem

*Introduced on [[Nehalem]]

*<tt>crc32</tt>

*<tt>pcmpestri</tt>

*<tt>pcmpestrm</tt>

*<tt>pcmpistri</tt>

*<tt>pcmpistrm</tt>

*<tt>pcmpgtq</tt>

*<tt>popcnt</tt>

===SSE4a (AMD)===

*<tt>lzcnt</tt>

*<tt>popcnt</tt>

*<tt>extrq</tt>

*<tt>insertq</tt>

*<tt>movntsd</tt>

*<tt>movntss</tt>

===SSE3 (PNI)===

*Originally known as Prescott New Instructions, and introduced on P4-Prescott

*<tt>[http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedProjects/instructions/instruct32_hh/movddup--move_one_double-fp_and_duplicate.htm movddup]</tt> -- move a double from a 8-byte-aligned memory location or lower half of XMM register to upper half, then duplicate upper half to lower half

*<tt>MWAIT/MONITOR</tt>

====SSSE3 (TNI/MNI)====

*Introduced with the Core microarchitecture. Sometimes referred to as Tejas New Instructions or Merom New Instructions

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===SSE2===

*Introduced with the P4.

*Extends the [[SIMD#MMX|MMX]] instructions to XMM registers.

*<tt>[http://www.sesp.cse.clrc.ac.uk/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc180.htm movapd]</tt> -- move two packed doubles from a 16-byte-aligned memory location to XMM registers, or vice versa, or between two XMM registers.

**<tt>[http://www.sesp.cse.clrc.ac.uk/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc205.htm movupd]</tt> -- <tt>movapd</tt> safe for unaligned memory references, with far inferior performance.

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===Future Directions===

* [http://software.intel.com/en-us/avx/ AVX] (Advanced Vector eXtensions) -- to be introduced on Intel's Sandy Bridge (2010) and AMD's Bulldozer (2011), and implemented within the [http://en.wikipedia.org/wiki/VEX_prefix VEX coding scheme]

* The [http://en.wikipedia.org/wiki/FMA_instruction_set FMA instruction set] extension to x86 should hit around 2011, providing floating-point fused multiply-add

** AMD appears to call this [http://en.wikipedia.org/wiki/FMA_instruction_set FMA4], part of what was SSE5

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* "[http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/61121/ Why no FMA in AVX in Sandy Bridge?]", Intel Developers Forum

* [http://developer.amd.com/cpu/SSE5/Pages/default.aspx SSE5] guide at AMD

* [http://softwarecommunity.intel.com/isn/Downloads/Intel%20SSE4%20Programming%20Reference.pdf SSE4] reference at Intel

* 2007-04-19 post to http://virtualdub.org, "[http://www.virtualdub.org/blog/pivot/entry.php?id=150 SSE4 finally adds dot products]"

* AMD64 Architecture Programmer’s Manual Volume 6: [http://support.amd.com/us/Processor_TechDocs/43479.pdf 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions]

* Agner Fog's [http://www.agner.org/optimize/instruction_tables.pdf x86 Instruction Tables]

* "[http://software.intel.com/en-us/blogs/2011/06/13/haswell-new-instruction-descriptions-now-available Haswell New Instruction Descriptions now Available]", Intel Software Developer Network, 2011-06-13

* General [[architecture]] page

[[Category: x86]]

@@ Line 1: / Line 1: @@
-First introduced on the Illiac IV, and not to be confused with vector processing.
+[[File:Simd.jpeg|thumb|right|A 4-way SIMD unit]]
+First introduced on the Illiac IV, and not to be confused with vector processing. SIMD-capable units are often taxonomized via <tt>SIMDnXm</tt> nomenclature, where '''n''' is the issue width and '''m''' is the channel width; a superscalar processor would be SIMDnX1, while a scalar SISD processor would be SIMD1X1.
+==Compilers and Assemblers==
+* [[GCC]] can issue SIMD four different ways:
+** [http://gcc.gnu.org/onlinedocs/gcc/Submodel-Options.html#Submodel-Options Target-specific code generation] will sometimes use scalar SIMD
+** [http://gcc.gnu.org/onlinedocs/gcc/Target-Builtins.html Target-specific builtins], using [http://gcc.gnu.org/onlinedocs/gcc/Vector-Extensions.html vector extensions]
+** [[GCC#Inline_Assembly|Inline assembly]], using syntax of the [http://sourceware.org/binutils/docs/as/index.html GNU Assembler] and a baroque register specification convention
+** [http://gcc.gnu.org/projects/tree-ssa/vectorization.html Auto-vectorization] from [[GCC|gcc's]] <tt>autovect</tt> branch attempts to autovectorize some loops
 ==Data Types (taken from SSE specs)==
-These do not necessarily map to the C data types of the same name, for any given compiler!
+These do not necessarily map to [[C]] data types of the same name, for any given compiler!
 * '''half precision''': 16-bit IEEE 754 floating-point (bias-15) (IEEE 754 2008 '''binary16''')
 * '''single''': 32-bit IEEE 754 floating-point (bias-127) (IEEE 754 2008 '''binary32''')
@@ Line 11: / Line 19: @@
 * '''doubleword''', '''dword''': 64-bit two's complement integer
+==x86 YMM==
+The [http://software.intel.com/en-us/avx/ AVX] (Advanced Vector eXtensions) were introduced on Intel's [[Sandy Bridge]] (2010) and AMD's [[Bulldozer]] (2011). They operate on the 256-bit YMM registers (YMM0..YMM15), which are aliased by the [[SIMD#x86_XMM|XMM]] registers. They are encoded using the [[VEX]] scheme. Support for AVX can be determined via:
+* Determine that [[CPUID]].1:ECX.OSXSAVE[bit 27] is set (XGETBV is enabled for application use)
+* Issue XGETBV and verify that XFEATURE_ENABLED_MASK[2:1] = 0x3 (XMM state and YMM state are enabled by OS)
+* Determine that [[CPUID]].1:ECX.AVX[bit 28] is set (AVX instructions supported)
+==x86 AVX==
+New 256-bit YMM registers.
+===New [[Haswell]] Instructions===
+* AVX2 instructions: integer SIMD using AVX's 256-bit YMM registers.
+* YMM-SIMD bit manipulation, permute, gather, shift, and FMA
+===AVX1===
+* Introduced on [[Sandy Bridge]]
 ==x86 XMM==
-The Streaming SIMD Extensions operate on the 128-bit XMM registers (XMM0..XMM7 in 32-bit mode, XMM0..XMM15 in 64-bit mode).
+The Streaming SIMD Extensions operate on the 128-bit XMM registers (XMM0..XMM7 in 32-bit mode, XMM0..XMM15 in 64-bit mode). In its original incarnation on the PIII, execution units (but not registers) were shared with the x87 floating-point architecture. The execution units were separated in the NetBurst microarchitecture. In the Core microarchitecture, the execution engine has been widened for greater SSE throughput.
 ===SSE5 (AMD)===
 * Unimplemented extensions competing with SSE4, encoded using a method incompatible with VEX
@@ Line 21: / Line 41: @@
 ===SSE4 (Intel)===
-====SSE4a====
 ====SSE4.1====
 [[File:Dppd.gif|thumb|DPPD instruction dataflow]]
@@ Line 30: / Line 49: @@
 ====SSE4.2====
-[[File:Intel Nehalem arch.png|thumb|Intel Nehalem microarchitecture]]
+[[File:Intel Nehalem arch.png|thumb|Intel [[Nehalem]] microarchitecture]]
-*Introduced on Nehalem
+*Introduced on [[Nehalem]]
+*<tt>crc32</tt>
+*<tt>pcmpestri</tt>
+*<tt>pcmpestrm</tt>
+*<tt>pcmpistri</tt>
+*<tt>pcmpistrm</tt>
+*<tt>pcmpgtq</tt>
+*<tt>popcnt</tt>
+===SSE4a (AMD)===
+*<tt>lzcnt</tt>
+*<tt>popcnt</tt>
+*<tt>extrq</tt>
+*<tt>insertq</tt>
+*<tt>movntsd</tt>
+*<tt>movntss</tt>
 ===SSE3 (PNI)===
 *Originally known as Prescott New Instructions, and introduced on P4-Prescott
 *<tt>[http://www.intel.com/software/products/documentation/vlin/mergedprojects/analyzer_ec/mergedprojects/reference_olh/mergedProjects/instructions/instruct32_hh/movddup--move_one_double-fp_and_duplicate.htm movddup]</tt> -- move a double from a 8-byte-aligned memory location or lower half of XMM register to upper half, then duplicate upper half to lower half
+*<tt>MWAIT/MONITOR</tt>
 ====SSSE3 (TNI/MNI)====
 *Introduced with the Core microarchitecture. Sometimes referred to as Tejas New Instructions or Merom New Instructions
@@ Line 42: / Line 76: @@
 ===SSE2===
+*Introduced with the P4.
+*Extends the [[SIMD#MMX|MMX]] instructions to XMM registers.
 *<tt>[http://www.sesp.cse.clrc.ac.uk/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc180.htm movapd]</tt> -- move two packed doubles from a 16-byte-aligned memory location to XMM registers, or vice versa, or between two XMM registers.
 **<tt>[http://www.sesp.cse.clrc.ac.uk/html/SoftwareTools/vtune/users_guide/mergedProjects/analyzer_ec/mergedProjects/reference_olh/mergedProjects/instructions/instruct32_hh/vc205.htm movupd]</tt> -- <tt>movapd</tt> safe for unaligned memory references, with far inferior performance.
@@ Line 55: / Line 91: @@
 ===Future Directions===
-* [http://software.intel.com/en-us/avx/ AVX] (Advanced Vector eXtensions) -- to be introduced on Intel's Sandy Bridge (2010) and AMD's Bulldozer (2011), and implemented within the [http://en.wikipedia.org/wiki/VEX_prefix VEX coding scheme]
 * The [http://en.wikipedia.org/wiki/FMA_instruction_set FMA instruction set] extension to x86 should hit around 2011, providing floating-point fused multiply-add
 ** AMD appears to call this [http://en.wikipedia.org/wiki/FMA_instruction_set FMA4], part of what was SSE5
@@ Line 74: / Line 109: @@
 * "[http://software.intel.com/en-us/forums/intel-avx-and-cpu-instructions/topic/61121/ Why no FMA in AVX in Sandy Bridge?]", Intel Developers Forum
 * [http://developer.amd.com/cpu/SSE5/Pages/default.aspx SSE5] guide at AMD
+* [http://softwarecommunity.intel.com/isn/Downloads/Intel%20SSE4%20Programming%20Reference.pdf SSE4] reference at Intel
 * 2007-04-19 post to http://virtualdub.org, "[http://www.virtualdub.org/blog/pivot/entry.php?id=150 SSE4 finally adds dot products]"
+* AMD64 Architecture Programmer’s Manual Volume 6: [http://support.amd.com/us/Processor_TechDocs/43479.pdf 128-Bit and 256-Bit XOP, FMA4 and CVT16 Instructions]
+* Agner Fog's [http://www.agner.org/optimize/instruction_tables.pdf x86 Instruction Tables]
+* "[http://software.intel.com/en-us/blogs/2011/06/13/haswell-new-instruction-descriptions-now-available Haswell New Instruction Descriptions now Available]", Intel Software Developer Network, 2011-06-13
+* General [[architecture]] page
 [[Category: x86]]

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