SMP on x86: Difference between revisions
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The primary specification for multiprocessor [[x86]]-based setups is the [http://www.intel.com/design/pentium/datashts/242016.HTM Intel MultiProcessor Specification] (last updated, AFAIK, to revision-006 on 1995-05-15). | The primary specification for multiprocessor [[x86]]-based setups is the [http://www.intel.com/design/pentium/datashts/242016.HTM Intel MultiProcessor Specification] (last updated, AFAIK, to revision-006 on 1995-05-15). | ||
==SMT== | |||
* HyperThreading (Intel SMT) requires CPU, BIOS and OS support. Introduced on the P4. | |||
** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding). | |||
** Pentium-M and Celerons usually lack SMT. | |||
* Unduplicated resources are either split or shared between logical cores: | |||
** Shared: reservation stations, data caches | |||
** Split: reorder buffers, load/store buffers | |||
** Duplicated: registers | |||
* No programmable priority control exported, no implicit priorities defined | |||
==Intel MP IDs== | |||
* Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID | |||
** The initial APIC ID can be retrieved via [[cpuid]], as can packaging data: | |||
*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured | |||
*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured | |||
*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel | |||
*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors | |||
*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore | |||
* APIC ID is formed of SMT_ID|CORE_ID|PACKAGE_ID, having widths defined by the packaging data: | |||
** SMT_ID is 0 bits on a non-HyperThreaded processor. | |||
** CORE_ID is 0 bits on a unicore package | |||
** All remaining bits are devoted to PACKAGE_ID | |||
==Interrupts== | ==Interrupts== | ||
* IO-APIC routes hardware interrupts to various CPUs ([http://www.mjmwired.net/kernel/Documentation/x86/i386/IO-APIC.txt Linux's IO-APIC.txt]) | * IO-APIC routes hardware interrupts to various CPUs ([http://www.mjmwired.net/kernel/Documentation/x86/i386/IO-APIC.txt Linux's IO-APIC.txt]) | ||
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MIS: 0 | MIS: 0 | ||
[recombinator](0) $ </pre> | [recombinator](0) $ </pre> | ||
==[[ACPI]] | ==Discovery== | ||
* [[ACPI]]'s MADT table can supply multiprocessor configuration, and is usually used if present | |||
* MP Table. The FreeBSD program <tt>mptable(1)</tt> can dump this: | * MP Table. The FreeBSD program <tt>mptable(1)</tt> can dump this: | ||
<pre>[bryhlath](0) $ sudo mptable | <pre>[bryhlath](0) $ sudo mptable | ||
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[bryhlath](0) $ </pre> | [bryhlath](0) $ </pre> | ||
==/proc/cpuinfo== | ==/proc/cpuinfo== | ||
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* The [[cpuid]] instruction can interrogate each processing unit | * The [[cpuid]] instruction can interrogate each processing unit | ||
* [[Cpuset|CPUsets]] | * [[Cpuset|CPUsets]] | ||
* "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network | |||
[[Category: x86]] | [[Category: x86]] | ||
[[CATEGORY: Hardware]] | |||