SMP on x86: Difference between revisions
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** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding). | ** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding). | ||
** Pentium-M and Celerons usually lack SMT. | ** Pentium-M and Celerons usually lack SMT. | ||
* | * Unduplicated resources are either split or shared between logical cores: | ||
** Shared: reservation stations, data caches | ** Shared: reservation stations, data caches | ||
** Split: reorder buffers, load/store buffers | ** Split: reorder buffers, load/store buffers | ||
** Duplicated: registers | |||
* No programmable priority control exported, no implicit priorities defined | |||
==Intel MP IDs== | ==Intel MP IDs== | ||
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* "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network | * "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network | ||
[[Category: x86]] | [[Category: x86]] | ||
[[CATEGORY: Hardware]] | |||