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[[File:Gt200die-big.jpg|right|thumb|A "Fermi" GT200 die]]
[[File:Gt200die-big.jpg|right|thumb|A "Fermi" GT200 die]]
==Hardware==
==Hardware==
NVIDIA maintains a list of [http://www.nvidia.com/object/cuda_learn_products.html supported hardware]. For actual hardware, you'll need the "nvidia.ko" kernel module. Download the <tt>nvidia-kernel-source</tt> and <tt>nvidia-kernel-common</tt> packages, unpack <tt>/usr/src/nvidia-kernel.tar.bz2</tt>, and run <tt>make-kpkg modules_image</tt>. Install the resulting .deb, and modprobe nvidia. You'll see something like this in dmesg output:<pre>nvidia: module license 'NVIDIA' taints kernel.
NVIDIA maintains a list of [http://www.nvidia.com/object/cuda_learn_products.html supported hardware]. You'll need the "nvidia.ko" kernel module. On [[Debian]], use the <tt>nvidia-kernel-dkms</tt> package to build a module appropriate for your kernel (and automatically rebuild it upon kernel upgrades). You can also download the <tt>nvidia-kernel-source</tt> and <tt>nvidia-kernel-common</tt> packages, unpack <tt>/usr/src/nvidia-kernel.tar.bz2</tt>, and run <tt>make-kpkg modules_image</tt>. Install the resulting .deb, and modprobe nvidia. You'll see something like this in dmesg output:<pre>nvidia: module license 'NVIDIA' taints kernel.
Disabling lock debugging due to kernel taint
Disabling lock debugging due to kernel taint
nvidia 0000:07:00.0: enabling device (0000 -> 0003)
nvidia 0000:07:00.0: enabling device (0000 -> 0003)
Line 7: Line 7:
nvidia 0000:07:00.0: setting latency timer to 64
nvidia 0000:07:00.0: setting latency timer to 64
NVRM: loading NVIDIA UNIX x86_64 Kernel Module  190.53  Wed Dec  9 15:29:46 PST 2009</pre>
NVRM: loading NVIDIA UNIX x86_64 Kernel Module  190.53  Wed Dec  9 15:29:46 PST 2009</pre>
Once the module is loaded, CUDA should be able to find the device. See [[CUDA#deviceQuery_Output|below]] for sample outputs.
Once the module is loaded, CUDA should be able to find the device. See [[CUDA#deviceQuery_Output|below]] for sample outputs. Each device has a [[CUDA#Compute_Capabilities|compute capability]], though this does not encompass all differentiated capabilities (see also <tt>deviceOverlap</tt> and <tt>canMapHostMemory</tt>...). Note that "emulation mode" has been removed as of CUDA Toolkit Version 3.1.
===Emulation===
Otherwise, there's emulation via the Runtime API (although this is deprecated, and going away!)...
<pre>[recombinator](0) $ ~/local/cuda/C/bin/linux/emurelease/deviceQuery
CUDA Device Query (Runtime API) version (CUDART static linking)
There is no device supporting CUDA.
 
Device 0: "Device Emulation (CPU)"
  CUDA Driver Version:                          2.30
  CUDA Runtime Version:                          2.30
  CUDA Capability Major revision number:        9999
  CUDA Capability Minor revision number:        9999
  Total amount of global memory:                4294967295 bytes
  Number of multiprocessors:                    16
  Number of cores:                              128
  Total amount of constant memory:              65536 bytes
  Total amount of shared memory per block:      16384 bytes
  Total number of registers available per block: 8192
  Warp size:                                    1
  Maximum number of threads per block:          512
  Maximum sizes of each dimension of a block:    512 x 512 x 64
  Maximum sizes of each dimension of a grid:    65535 x 65535 x 1
  Maximum memory pitch:                          262144 bytes
  Texture alignment:                            256 bytes
  Clock rate:                                    1.35 GHz
  Concurrent copy and execution:                No
  Run time limit on kernels:                    No
  Integrated:                                    Yes
  Support host page-locked memory mapping:      Yes
  Compute mode:                                  Default (multiple host threads can use this device simultaneously)
 
Test PASSED</pre>
Each device has a '''compute capability''', though this does not encompass all differentiated capabilities (see also <tt>deviceOverlap</tt> and <tt>canMapHostMemory</tt>...).


==CUDA model==
==CUDA model==
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** Larger one-time setup cost due to device register programming for DMA transfers.
** Larger one-time setup cost due to device register programming for DMA transfers.
** This memory will be unswappable -- allocate only as much as is needed.
** This memory will be unswappable -- allocate only as much as is needed.
* Pinned memory can be mapped directly into CUDAspace on ''integrated'' devices or in the presence of some IOMMUs.
* Pinned memory can be mapped directly into CUDAspace on ''integrated'' devices or in the presence of some [[IOMMU|IOMMUs]].
** "Zero (explicit)-copy" interface (can never hide all bus delays)
** "Zero (explicit)-copy" interface (can never hide all bus delays)
* Write-combining memory (configured via [[MTRR|MTRRs]] or [[Page Attribute Tables|PATs]]) avoids PCI snoop requirements and maximizes linear throughput
* Write-combining memory (configured via [[MTRR|MTRRs]] or [[Page Attribute Tables|PATs]]) avoids PCI snoop requirements and maximizes linear throughput
Line 64: Line 32:
===Streaming Multiprocessor===
===Streaming Multiprocessor===
* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor|Stream Processors]] (SPs).
* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor|Stream Processors]] (SPs).
** 8192 registers for compute capability <= 1.1, otherwise
** 8K registers for compute capability <= 1.1, otherwise
** 16384 for compute capability <= 1.3
** 16K for compute capability <= 1.3, otherwise
** 32K for compute capability <= 2.1, otherwise
** 64K through at least compute capability 3.5
* A group of threads which share a memory and can "synchronize their execution to coördinate accesses to memory" (use a [[barrier]]) form a '''block'''. Each thread has a ''threadId'' within its (three-dimensional) block.
* A group of threads which share a memory and can "synchronize their execution to coördinate accesses to memory" (use a [[barrier]]) form a '''block'''. Each thread has a ''threadId'' within its (three-dimensional) block.
** For a block of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>, D<sub>z</sub>&gt;, the threadId of the thread having index &lt;x, y, z&gt; is (x + y * D<sub>x</sub> + z * D<sub>y</sub> * D<sub>x</sub>).
** For a block of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>, D<sub>z</sub>&gt;, the threadId of the thread having index &lt;x, y, z&gt; is (x + y * D<sub>x</sub> + z * D<sub>y</sub> * D<sub>x</sub>).
* Register allocation is performed per-block, and rounded up to the nearest
* Register allocation is performed per-block, and rounded up to the nearest
** 256 registers per block for compute capability <= 1.1, otherwise
** 256 registers per block for compute capability <= 1.1, otherwise
** 512 registers per block for compute capability <= 1.3.
** 512 registers per block for compute capability <= 1.3
* A group of blocks which share a kernel form a '''grid'''. Each block (and each thread within that block) has a ''blockId'' within its (two-dimensional) grid.
* A group of blocks which share a kernel form a '''grid'''. Each block (and each thread within that block) has a ''blockId'' within its (two-dimensional) grid.
** For a grid of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>&gt;, the blockId of the block having index &lt;x, y&gt; is (x + y * D<sub>x</sub>).
** For a grid of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>&gt;, the blockId of the block having index &lt;x, y&gt; is (x + y * D<sub>x</sub>).
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===Stream Processor===
===Stream Processor===
* In-order, multithreaded processor: memory latencies can be hidden only by TLP, not ILP.
* In-order, multithreaded processor: memory latencies can be hidden only by TLP, not ILP.
** '''UPDATE''' Vasily Volkov's awesome GTC 2010 paper, "[http://www.cs.berkeley.edu/~volkov/volkov10-GTC.pdf Better Performance at Lower Occupancy]", ''destroys'' this notion.
*** Really. Go read Vasily's paper. It's better than anything you'll find here.
** Arithmetic intensity and parallelism are paramount!
** Arithmetic intensity and parallelism are paramount!
** Memory-bound kernels require sufficiently high ''occupancy'' (the ratio of concurrently-running warps to maximum possible concurrent warps (as applied, usually, to [[#Streaming Multiprocessor|SMs]])) to hide latency.
** Memory-bound kernels require sufficiently high ''occupancy'' (the ratio of concurrently-running warps to maximum possible concurrent warps (as applied, usually, to [[#Streaming Multiprocessor|SMs]])) to hide latency.
* No branch prediction or speculation (and thus also no pipeline flushes on mispredicted branches).
* No branch prediction or speculation. Full predication.
{| border="1"
{| border="1"
! Memory type
! Memory type
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| Read-write
| Read-write
| Read-write
| Read-write
| None
| '''1.x''': None
'''2.0+''': L1 on SM, L2 on TPC(?)
| Yes
| Yes
|-
|-
Line 192: Line 165:


===Compute Capabilities===
===Compute Capabilities===
The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been backwards-compatible.
The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been fowards-compatible, though recent CUDA toolkits will not generate code for CC1 or 2.
 
{| border="1" class="wikitable"
! Resource
! 1.0 SM
! 1.1 SM
! 1.2 SM
! 1.3 SM
! 2.0 SM
! 2.1 SM
! 3.0 SMX
! 3.5 SMX
! 7.0 SM
! 7.5 SM
|-
|CUDA cores
|8
|8
|8
|8
|32
|48
|192
|192
|64/32<br/>64/8
|64/2<br/>64/8
|-
|Schedulers
|1
|1
|1
|1
|2
|2
|4
|4
|4
|4
|-
|Insts/sched
|1
|1
|1
|1
|1
|2
|2
|2
|1
|1
|-
|Threads
|768
|768
|1K
|1K
|1536
|1536
|2K
|2K
|2K
|1K
|-
|Warps
|24
|24
|32
|32
|48
|48
|64
|64
|64
|32
|-
|Blocks
|8
|8
|8
|8
|8
|8
|16
|16
|32
|16
|-
|32-bit regs
|8K
|8K
|16K
|16K
|32K
|32K
|64K
|64K
|64K
|64K
|-
|Examples
|G80
|G9x
|GT21x
|GT200
|GF110
|GF10x
|GK104
|GK110
|GV100
|TU10x
|-
|}
{| border="1"
{| border="1"
! Revision
! Revision
Line 216: Line 300:
| 2.0
| 2.0
|
|
* 32 cores per SM
* 4 SFUs
* Atomic addition on 32-bit global and shared FP.
* Atomic addition on 32-bit global and shared FP.
* 48 warps (1536 threads), 48K shared memory banked 32 ways, and 32K registers per MP.
* 48 warps (1536 threads), 48K shared memory banked 32 ways, and 32K registers per MP.
Line 222: Line 308:
* 1024 threads per block and <tt>blockIdx.{x,y}</tt> values ranging through 1024.
* 1024 threads per block and <tt>blockIdx.{x,y}</tt> values ranging through 1024.
* Larger texture references.
* Larger texture references.
* PTX 2.0
* ''PTX 2.0''
** Efficient uniform addressing (<tt>ldu</tt>)
** Efficient uniform addressing (<tt>ldu</tt>)
** Unified address space: <tt>isspacep</tt>/<tt>cvta</tt>
** Unified address space: <tt>isspacep</tt>/<tt>cvta</tt>
Line 231: Line 317:
** New special registers: <tt>nsmid</tt>, <tt>clock64</tt>, ...).
** New special registers: <tt>nsmid</tt>, <tt>clock64</tt>, ...).
|-
|-
|}
| 2.1
|
* 48 cores per SM
* 8 SFUs per SM, 8 TFUs per ROP
* 2 warp schedulers per SM, capable of issuing two instructions per clock
|-
| 3.0
|
* 192 cores per SMX
* 32 SFUs per SMX, 32 TFUs per ROP
* 4 warp schedulers per SMX, capable of issuing two instructions per clock
* Double-precision instructions can be paired with non-DP
** Previously, double-precision instructions couldn't be paired with anything
* ''PTX 3.0''
** <tt>madc</tt> and <tt>mad.cc</tt> instructions
** Cubemaps and cubearrays for the <tt>tex</tt> instruction
** 3D surfaces via the <tt>suld.b.3d</tt> and <tt>sust.b.3d</tt> instructions
** <tt>pmevent.mask</tt> to trigger multiple performance counters
** 64-bit grid IDs
** 4 more performance counters, for a total of 8
** DWARF debugging symbols support


==Installation on [[Debian]]==
|-
[http://packages.debian.org/sid/libdevel/libcuda1-dev libcuda-dev] packages exist in the <tt>non-free</tt> archive area, and supply the core library <tt>libcuda.so</tt>. Together with the upstream toolkit and SDK from NVIDIA, this provides a full CUDA development environment for 64-bit Debian Unstable systems. I installed CUDA 2.3 on 2010-01-25 (hand-rolled 2.6.32.6 kernel, built with gcc-4.4). This machine did not have CUDA-compatible hardware (it uses [[Intel 965]]).
| 3.5
* Download the Ubuntu 9.04 files from NVIDIA's "[http://www.nvidia.com/object/cuda_get.html CUDA Zone]".
|
* Run the toolkit installer (<tt>sh cudatoolkit_2.3_linux_64_ubuntu9.04.run</tt>)
* 255 registers per thread
** For a user-mode install, supply <tt>$HOME/local</tt> or somesuch
* "CUDA Dynamic Parallelism", the ability to spawn threads from within device code
<pre>* Please make sure your PATH includes /home/dank/local/cuda/bin
* ''PTX 3.1''
* Please make sure your LD_LIBRARY_PATH
** A funnel shift instruction, <tt>shf</tt>
*   for 32-bit Linux distributions includes /home/dank/local/cuda/lib
** Loading read-only global data through the non-coherent texture cache, <tt>ld.global.nc</tt>
*   for 64-bit Linux distributions includes /home/dank/local/cuda/lib64
** 64-bit atomic/reduction operators extended to {or, xor, and, integer min, integer max}
* OR
** Mipmap type support
*   for 32-bit Linux distributions add /home/dank/local/cuda/lib
** Indirect texture/surface support
*   for 64-bit Linux distributions add /home/dank/local/cuda/lib64
** Extends generic addressing to include the const state space
* to /etc/ld.so.conf and run ldconfig as root


* Please read the release notes in /home/dank/local/cuda/doc/
|-
| 7.0
|
* ''PTX 6.3''
* Tensor cores
* Independent thread scheduling


* To uninstall CUDA, delete /home/dank/local/cuda
|-
* Installation Complete</pre>
| 7.5
* Run the SDK installer (<tt>sh cudasdk_2.3_linux.run</tt>)
|
** I just installed it to the same directory as the toolkit, which seems to work fine.
* ''PTX 6.4''
<pre>========================================
* Integer matrix multiplication in tensor cores
|-
|}


Configuring SDK Makefile (/home/dank/local/cuda/shared/common.mk)...
==PTX==
===Syntax Coloring===
[[File:ptxcolor.png|thumb|right|PTX with syntax coloring]]
I've got a [[vim]] syntax coloring file for PTX/NVIR/SASS at https://raw.github.com/dankamongmen/dankhome/master/.vim/syntax/nvir.vim. It operates by coloring all registers congruent to some integer mod 10 the same color:
<pre>syn match asmReg0 "v\?R[0-9]*0\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg1 "v\?R[0-9]*1\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg2 "v\?R[0-9]*2\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg3 "v\?R[0-9]*3\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg4 "v\?R[0-9]*4\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg5 "v\?R[0-9]*5\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg6 "v\?R[0-9]*6\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg7 "v\?R[0-9]*7\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg8 "v\?R[0-9]*8\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmReg9 "v\?R[0-9]*9\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmPReg "P[0-9]\([0-9]*\)\(\.B\|\.F\|\.U\?\(I\|L\)\|\([^0-9]\)\@=\)"
syn match asmBB "BB[0-9][0-9]*\(_\d\d*\)\?"
syn match asmBBNew "BB-\d\d*"
syn match nvirNT ".NEXT_TRUE.*"
syn match nvirNF ".NEXT_FALSE.*"
syn match hexconst "0x\x\+\(\.F\|\.U\?\(I\|L\)\)\?"
syn match spreg "\(ctaid\|ntid\|tid\|nctaid\).\(x\|y\|z\)"</pre>


========================================
* Please make sure your PATH includes /home/dank/local/cuda/bin
* Please make sure your LD_LIBRARY_PATH includes /home/dank/local/cuda/lib
* To uninstall the NVIDIA GPU Computing SDK, please delete /home/dank/local/cuda
* Installation Complete</pre>
==Building CUDA Apps==
==Building CUDA Apps==
===nvcc flags===
===nvcc flags===
* <tt>-ptax-options=-v</tt> displays per-thread register usage
Pass flags to <tt>ptxas</tt> via -X:
* <tt>-X -v</tt> displays per-thread register usage
* <tt>-X -abi=no</tt> disables the PTX ABI, saving registers but taking away your stack
* <tt>-dlcm={cg,cs,ca}</tt> modifies cache behavior for loads
* <tt>-dscm={cw,cs}</tt> modifies cache behavior for stores
===SDK's common.mk===
===SDK's common.mk===
This assumes use of the SDK's common.mk, as recommended by the documentation.
This assumes use of the SDK's common.mk, as recommended by the documentation.
Line 318: Line 447:
* A run time limit is activated by default if the device is being used to drive a display.
* A run time limit is activated by default if the device is being used to drive a display.
* Please feel free to [mailto:nickblack@acm.org send me output!]
* Please feel free to [mailto:nickblack@acm.org send me output!]
{| border="1"
{| border="1"
! Device name
! Device name
Line 323: Line 454:
! MP's
! MP's
! Cores
! Cores
! Const mem
! Shmem/block
! Shmem/block
! Reg/block
! Reg/block
! Warp size
! Warp size
! Thr/block
! Thr/block
! Max pitch
! Texalign
! Texalign
! Clock
! Clock
Line 335: Line 464:
! Shared maps?
! Shared maps?
|-
|-
! COLSPAN="15" style="background:#ffdead;" | Compute capability 2.0
! COLSPAN="13" style="background:#eebeb6;" | Compute capability 7.0
|-
|-
| Tesla C2050
| Tesla V100
| 3GB
| 16GB
|
| 84
|
| 5376/2688/672
|
|
|
|  
|  
|  
|  
|  
|
|
|  
|  
|  
|  
| 1.53GHz
| Yes
| No
| Yes
|-
! COLSPAN="13" style="background:#8070D8;" | Compute capability 3.0
|-
| GeForce GTX 680
| 1.5GB
| 8
| 1536
|  
|  
|
|
|
|
|
| Yes
| No
| Yes
|-
! COLSPAN="13" style="background:#ffdead;" | Compute capability 2.1
|-
| GeForce GTX 560 Ti
|
|
|
|
|
|
|
|
|
|
|
|
|-
| GeForce GTX 550 Ti
|
|
|
|
|
|
|
|
|
|
|
|
|-
| GeForce GTX 460
| 1GB
| 7
| 224
| 48k
| 32k
| 32
| 1024
| 512b
| 1.35GHz
| Yes
| No
| Yes
|-
| GeForce GTS 450
|
|
|
|
|
|
|
|
|
|
|
|
|
|-
|-
| Tesla C2070
! COLSPAN="13" style="background:#ffdead;" | Compute capability 2.0
| 6GB
|-
|
| GeForce GTX 580
|
| 1.5GB
|
| 16
|
| 512
|
|
|
|  
|  
|  
|  
|  
|  
|
|
| 32
| 1024
|
|
| 1.544GHz
| Yes
| No
| Yes
|-
| Tesla C2050 (*CB)
| 3GB
| 14
| 448
| 48k
| 32k
| 32
| 1024
| 512b
| 1.15GHz
| Yes
| No
| Yes
|-
| Tesla C2070 (*CB)
| 6GB
| 14
| 448
| 48k
| 32k
| 32
| 1024
| 512b
| 1.15GHz
| Yes
| No
| Yes
|-
|-
| GeForce GTX 480
| GeForce GTX 480
|  
| 1536MB
|  
| 15
|  
| 480
|
|
|  
|  
|  
|  
Line 387: Line 613:
|-
|-
| GeForce GTX 470
| GeForce GTX 470
|  
| 1280MB
|  
| 14
|  
| 448
|
|
|  
|  
|  
|  
Line 402: Line 626:
|
|
|-
|-
! COLSPAN="15" style="background:#efefef;" | Compute capability 1.3
! COLSPAN="13" style="background:#efefef;" | Compute capability 1.3
|-
|-
| Tesla C1060
| Tesla C1060
Line 408: Line 632:
| 30
| 30
| 240
| 240
| 65536b
| 16384b
| 16384b
| 16384
| 16384
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.30GHz
| 1.30GHz
Line 424: Line 646:
| 30
| 30
| 240
| 240
| 65536b
| 16384b
| 16384b
| 16384
| 16384
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.24GHz
| 1.24GHz
Line 440: Line 660:
| 30
| 30
| 240
| 240
| 65536b
| 16384b
| 16384b
| 16384
| 16384
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.48GHz
| 1.48GHz
| Yes
| Yes
| Yes
| No
| Yes
| Yes
|-
|-
Line 456: Line 674:
| 30
| 30
| 240
| 240
| 65536b
| 16384b
| 16384b
| 16384
| 16384
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.30GHz
| 1.30GHz
Line 472: Line 688:
| 27
| 27
| 216
| 216
| 65536b
| 16384b
| 16384b
| 16384
| 16384
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.47GHz
| 1.47GHz
Line 484: Line 698:
| Yes
| Yes
|-
|-
! COLSPAN="15" style="background:#efefef;" | Compute capability 1.2
! COLSPAN="13" style="background:#efefef;" | Compute capability 1.2
|-
|-
| GeForce GT 360M
| GeForce GT 360M
Line 490: Line 704:
| 12
| 12
| 96
| 96
| 65536b
| 16384b
| 16384b
| 16384
| 16384
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.32GHz
| 1.32GHz
Line 506: Line 718:
| 2
| 2
| 16
| 16
| 65536b
| 16384b
| 16384b
| 16384
| 16384
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.40GHz
| 1.40GHz
Line 522: Line 732:
| 12
| 12
| 96
| 96
| 65536b
| 16384b
| 16384b
| 16384
| 16384
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.424GHz
| 1.424GHz
Line 534: Line 742:
| Yes
| Yes
|-
|-
! COLSPAN="15" style="background:#efefef;" | Compute capability 1.1
! COLSPAN="13" style="background:#efefef;" | Compute capability 1.1
|-
|-
| ION
| ION
Line 540: Line 748:
| 2
| 2
| 16
| 16
| 65536b
| 16384b
| 16384b
| 8192
| 8192
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.1GHz
| 1.1GHz
Line 556: Line 762:
| 2
| 2
| 16
| 16
| 65536b
| 16384b
| 16384b
| 8192
| 8192
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 0.92GHz
| 0.92GHz
| Yes
| No
| No
|-
| GeForce GTS 250 (*JR)
| 1G
| 16
| 128
| 16384b
| 8192
| 32
| 512
| 256b
| 1.84GHz
| Yes
| Yes
| No
| No
Line 572: Line 790:
| 16
| 16
| 128
| 128
| 65536b
| 16384b
| 16384b
| 8192
| 8192
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.67GHz
| 1.67GHz
Line 588: Line 804:
| 8
| 8
| 64
| 64
| 65536b
| 16384b
| 16384b
| 8192
| 8192
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.62GHz,
| 1.62GHz,
Line 605: Line 819:
| 2
| 2
| 16
| 16
| 65536b
| 16384b
| 16384b
| 8192
| 8192
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 0.88GHz
| 0.88GHz
Line 621: Line 833:
| 16
| 16
| 128
| 128
| 65536b
| 16384b
| 16384b
| 8192
| 8192
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.62GHz
| 1.62GHz
Line 637: Line 847:
| 4
| 4
| 32
| 32
| 65536b
| 16384b
| 16384b
| 8192
| 8192
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 0.95GHz
| 0.95GHz
Line 653: Line 861:
| 1
| 1
| 8
| 8
| 65536b
| 16384b
| 16384b
| 8192
| 8192
| 32
| 32
| 512
| 512
| 262144b
| 256b
| 256b
| 1.40GHz
| 1.40GHz
Line 666: Line 872:
|-
|-
|}
|}
(*CB) Thanks to Cameron Black for this submission!
(*JR) Thanks to Javier Ruiz for this submission!


==See Also==
==See Also==
Retrieved from "https://nick-black.com/dankwiki/index.php?title=CUDA"