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Microarchitectures: Difference between revisions

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Line 22: Line 22:
| 16
| 16
| 20
| 20
| 4.77--10 MHz
| 4--10 MHz
| x86-16
| x86-16
| Segmented memory
| Segmented memory<br/>Optional 80-bit 8087 FP coprocessor
Optional 80-bit 8087 FP coprocessor
|-
|-
| 8088
| 8088
Line 35: Line 34:
| 16/8
| 16/8
| 20
| 20
| 4.77--10 MHz
| 5--8 MHz
| x86-16
| x86-16
| Designed for use with 8-bit externals
| Designed for use with 8-bit externals<br/>Used in IBM PC-5150 / XT-5160 / PCjr-4860
Used in IBM PC-5150 / XT-5160 / PCjr-4860
|-
|-
| 80186
| 80186
Line 59: Line 57:
| 24
| 24
| 4--12.5 MHz
| 4--12.5 MHz
| 8086-2
| 8086-2<br/>+ PVAM
| Introduced protected mode/MMU
| Introduced protected mode/MMU<br/>Used in the IBM AT-5170
Used in the IBM AT-5170
|-
|-
| 80386-DX
| 80386-DX
Line 84: Line 81:
| x86-32
| x86-32
| Optional 80387SX (16-bit) FP
| Optional 80387SX (16-bit) FP
|-
| 80376
| Intel
| 1989
| CHMOS IV 1 µm
| PQFP-100<br/>PGA-88
| 32/16
| 24
| 16--20
| x86-32
| Protected mode '''only'''<br/>No paging<br/>Optional 80387SX (16-bit) FP
|-
|-
| 80386-SL
| 80386-SL
Line 100: Line 108:
* x86-16: The granddaddy of 'em all
* x86-16: The granddaddy of 'em all
* 8086-2: Added ENTER/LEAVE, PUSHA/POPA, INS/OUTS
* 8086-2: Added ENTER/LEAVE, PUSHA/POPA, INS/OUTS
* PVAM: Added Protected Virtual Address Mode instructions (L/S*DT, etc)
===Physical Packages===
===Physical Packages===
* DIP (dual in-line package): 2 parallel rows of pins
* DIP (dual in-line package): 2 parallel rows of pins
Line 111: Line 120:
* [http://portfolio.ecs.soton.ac.uk/29/1/Intel_History.pdf An Outline of Developments in Intel CPU Architecture], Benjamin MJ Hodgson, University of Southampton, 2007-03-14
* [http://portfolio.ecs.soton.ac.uk/29/1/Intel_History.pdf An Outline of Developments in Intel CPU Architecture], Benjamin MJ Hodgson, University of Southampton, 2007-03-14
* [http://www.redhill.net.au/c/c-1.html The Red Hill CPU Guide], Red Hill Technology
* [http://www.redhill.net.au/c/c-1.html The Red Hill CPU Guide], Red Hill Technology
* [[Media:8088 datasheet.pdf|Intel 8088 Datasheet]], Intel, 1990-08
* [http://www.ragestorm.net/downloads/286intel.txt Intel 80286 Programmer's Reference Manual], Intel, 1987
* [http://www.ragestorm.net/downloads/286intel.txt Intel 80286 Programmer's Reference Manual], Intel, 1987
* [[Media:Intel_80387_Datasheet.PDF|Intel 80376 Datasheet]], Intel, 1990-12
* [[Media:Amd80186.pdf|80186 AMD Datasheet]], Advanced Micro Devices, 1991-11-01
* [[Media:Amd80186.pdf|80186 AMD Datasheet]], Advanced Micro Devices, 1991-11-01
* [http://www.intersil.com/design/packages/hermetic.asp Hermetic Package information], Intersil
* [http://www.intersil.com/design/packages/hermetic.asp Hermetic Package information], Intersil
* [http://www.evergreensemiconductor.com/products/packages Packages], Evergreen Semiconductor Materials
* [http://www.evergreensemiconductor.com/products/packages Packages], Evergreen Semiconductor Materials
* [http://www.cpu-world.com/CPUs/ Microprocessor/Co-processor/Microcontroller families], CPU World
* [http://www.cpu-world.com/CPUs/ Microprocessor/Co-processor/Microcontroller families], CPU World
 
* [http://www.pagetable.com/?p=460 The Intel 80376 – a Legacy-Free i386 (with a Twist!)], pagetable.com, 2010-11-16
[[CATEGORY: Hardware]]
[[CATEGORY: Hardware]]
[[CATEGORY: x86]]
[[CATEGORY: x86]]

Latest revision as of 01:31, 31 August 2012

Microarchitecture is defined as those elements of a CPU design which are, to first order, invisible to application programmers (ie, not part of the instruction set). Those elements which are visible comprise the architecture.

x86 μarchitectures

FIXME: add early clones (NEC V20/V30, etc), AMD, VIA, Cyrix etc...
FIXME: add variants (80188, embedded 80386's, etc)

Name Maker Date Process (min) Package ALU/data bits Addr bits Clock(s) ISA Notes
8086 Intel 1978 3.2 μm 40-pin DIP 16 20 4--10 MHz x86-16 Segmented memory
Optional 80-bit 8087 FP coprocessor
8088 Intel 1979 3.2 μm (?) 40-pin DIP

44-pin PLCC

16/8 20 5--8 MHz x86-16 Designed for use with 8-bit externals
Used in IBM PC-5150 / XT-5160 / PCjr-4860
80186 Intel 1980 2.6 μm 68-pin PLCC
68-pin PGA
100-pin PQFP 		16 20 6--25 MHz 8086-2 Designed for embedded systems
(clock, PIC, DMA on-die)
80286 Intel 1982 1.5 μm 68-pin PGA
68-pin CLCC
68-pin PLCC 		16 24 4--12.5 MHz 8086-2
+ PVAM 		Introduced protected mode/MMU
Used in the IBM AT-5170
80386-DX Intel 1985 CHMOS III 1.5 µm
CHMOS IV 1 µm 		132-pin PGA
132-pin PQFP 		32 32 12--33 MHz x86-32 Introduced paging, VM86, flat memory
Optional 80287 or 80387 FP
Support for external caches
80386-SX Intel 1988 CHMOS IV 1 µm PQFP-100
PGA-88 		32/16 24 16--33 MHz x86-32 Optional 80387SX (16-bit) FP
80376 Intel 1989 CHMOS IV 1 µm PQFP-100
PGA-88 		32/16 24 16--20 x86-32 Protected mode only
No paging
Optional 80387SX (16-bit) FP
80386-SL Intel 1990 CHMOS IV 1 µm PQFP-132 32/16 24 20--25 MHz x86-32 Designed for mobile/low-power systems
Added System Management Mode

Instruction sets

  • x86-16: The granddaddy of 'em all
  • 8086-2: Added ENTER/LEAVE, PUSHA/POPA, INS/OUTS
  • PVAM: Added Protected Virtual Address Mode instructions (L/S*DT, etc)

Physical Packages

  • DIP (dual in-line package): 2 parallel rows of pins
  • PGA (pin grid array): Regularly-spaced pins in rectangular geometry
  • CLCC (ceramic leadless chip carrier): Regularly-spaced metallized castellations in rectangular geometry
  • PLCC (plastic lead chip carrier): Regularly-spaced J-leads in rectangular geometry, surface- or package-mounted
  • PQFP (plastic quad flat pack): Regularly-spaced side leads in rectangular geometry, designed for surface mounting

References

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