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kill const memory size column, add V100
"65K" ?!
 
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nvidia 0000:07:00.0: setting latency timer to 64
nvidia 0000:07:00.0: setting latency timer to 64
NVRM: loading NVIDIA UNIX x86_64 Kernel Module  190.53  Wed Dec  9 15:29:46 PST 2009</pre>
NVRM: loading NVIDIA UNIX x86_64 Kernel Module  190.53  Wed Dec  9 15:29:46 PST 2009</pre>
Once the module is loaded, CUDA should be able to find the device. See [[CUDA#deviceQuery_Output|below]] for sample outputs. Each device has a '''compute capability''', though this does not encompass all differentiated capabilities (see also <tt>deviceOverlap</tt> and <tt>canMapHostMemory</tt>...). Note that "emulation mode" has been removed as of CUDA Toolkit Version 3.1.
Once the module is loaded, CUDA should be able to find the device. See [[CUDA#deviceQuery_Output|below]] for sample outputs. Each device has a [[CUDA#Compute_Capabilities|compute capability]], though this does not encompass all differentiated capabilities (see also <tt>deviceOverlap</tt> and <tt>canMapHostMemory</tt>...). Note that "emulation mode" has been removed as of CUDA Toolkit Version 3.1.


==CUDA model==
==CUDA model==
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===Streaming Multiprocessor===
===Streaming Multiprocessor===
* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor|Stream Processors]] (SPs).
* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor|Stream Processors]] (SPs).
** 8192 registers for compute capability <= 1.1, otherwise
** 8K registers for compute capability <= 1.1, otherwise
** 16384 for compute capability <= 1.3, otherwise
** 16K for compute capability <= 1.3, otherwise
** 32768 for compute capability <= 2.1, otherwise
** 32K for compute capability <= 2.1, otherwise
** 65k through at least compute capability 3.5
** 64K through at least compute capability 3.5
* A group of threads which share a memory and can "synchronize their execution to coördinate accesses to memory" (use a [[barrier]]) form a '''block'''. Each thread has a ''threadId'' within its (three-dimensional) block.
* A group of threads which share a memory and can "synchronize their execution to coördinate accesses to memory" (use a [[barrier]]) form a '''block'''. Each thread has a ''threadId'' within its (three-dimensional) block.
** For a block of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>, D<sub>z</sub>&gt;, the threadId of the thread having index &lt;x, y, z&gt; is (x + y * D<sub>x</sub> + z * D<sub>y</sub> * D<sub>x</sub>).
** For a block of dimensions &lt;D<sub>x</sub>, D<sub>y</sub>, D<sub>z</sub>&gt;, the threadId of the thread having index &lt;x, y, z&gt; is (x + y * D<sub>x</sub> + z * D<sub>y</sub> * D<sub>x</sub>).
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===Compute Capabilities===
===Compute Capabilities===
The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been backwards-compatible.
The original public CUDA revision was 1.0, implemented on the NV50 chipset corresponding to the GeForce 8 series. Compute capability, formed of a non-negative major and minor revision number, can be queried on CUDA-capable cards. All revisions thus far have been fowards-compatible, though recent CUDA toolkits will not generate code for CC1 or 2.
 
{| border="1" class="wikitable"
{| border="1" class="wikitable"
! Resource
! Resource
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! 3.0 SMX
! 3.0 SMX
! 3.5 SMX
! 3.5 SMX
! 7.0 SM
! 7.5 SM
|-
|-
|CUDA cores
|CUDA cores
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|192
|192
|192
|192
|64/32<br/>64/8
|64/2<br/>64/8
|-
|-
|Warp schedulers
|Schedulers
|1
|1
|1
|1
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|2
|2
|2
|2
|4
|4
|4
|4
|4
|4
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|2
|2
|2
|2
|1
|1
|-
|-
|Threads
|Threads
|768
|768
|768
|768
|1024
|1K
|1024
|1K
|1536
|1536
|1536
|1536
|2048
|2K
|2048
|2K
|2K
|1K
|-
|-
|Warps
|Warps
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|64
|64
|64
|64
|64
|32
|-
|-
|Blocks
|Blocks
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|8
|8
|16
|16
|16
|32
|16
|16
|-
|-
|32-bit registers
|32-bit regs
|8192
|8K
|8192
|8K
|16384
|16K
|16384
|16K
|32768
|32K
|32768
|32K
|65536
|64K
|65536
|64K
|64K
|64K
|-
|-
|Example chips
|Examples
|
|G80
|
|G9x
|
|GT21x
|  
|GT200
| GF100
|GF110
| GF104/GF106/GF108
|GF10x
| GK104
|GK104
| GK110
|GK110
|GV100
|TU10x
|-
|-
}
|}
{| border="1"
{| border="1"
! Revision
! Revision
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** Indirect texture/surface support
** Indirect texture/surface support
** Extends generic addressing to include the const state space
** Extends generic addressing to include the const state space
|-
| 7.0
|
* ''PTX 6.3''
* Tensor cores
* Independent thread scheduling
|-
| 7.5
|
* ''PTX 6.4''
* Integer matrix multiplication in tensor cores
|-
|-
|}
|}
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