SMP on x86

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The primary specification for multiprocessor [[x86]]-based setups is the [http://www.intel.com/design/pentium/datashts/242016.HTM Intel MultiProcessor Specification] (last updated, AFAIK, to revision-006 on 1995-05-15).

==SMT==

* HyperThreading (Intel SMT) requires CPU, BIOS and OS support. Introduced on the P4.

** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).

** Pentium-M and Celerons usually lack SMT.

* Unduplicated resources are either split or shared between logical cores:

** Shared: reservation stations, data caches

** Split: reorder buffers, load/store buffers

** Duplicated: registers

* No programmable priority control exported, no implicit priorities defined

==Intel MP IDs==

* Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID

** The initial APIC ID can be retrieved via [[cpuid]], as can packaging data:

*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured

*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured

*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel

*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors

*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore

* APIC ID is formed of SMT_ID|CORE_ID|PACKAGE_ID, having widths defined by the packaging data:

** SMT_ID is 0 bits on a non-HyperThreaded processor.

** CORE_ID is 0 bits on a unicore package

** All remaining bits are devoted to PACKAGE_ID

==Interrupts==

* IO-APIC routes hardware interrupts to various CPUs ([http://www.mjmwired.net/kernel/Documentation/x86/i386/IO-APIC.txt Linux's IO-APIC.txt])

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MIS: 0

[recombinator](0) $ </pre>

==[[ACPI]]==

==Discovery==

* The MADT table can supply multiprocessor configuration

* [[ACPI]]'s MADT table can supply multiprocessor configuration, and is usually used if present

* MP Table

* MP Table. The FreeBSD program <tt>mptable(1)</tt> can dump this:

* Interactions with [~~[cpuid]~~]

<pre>[bryhlath](0) $ sudo mptable

* HyperThreading (~~Intel SMT~~) ~~requires CPU,~~ BIOS ~~and OS support~~. ~~Introduced on the P4~~.

** Found on (all) i7's, ~~[http~~://~~www.intel.com/technology/atom/microarchitecture.htm some Atoms~~]~~, and some P4's and Core2Duo's~~ (~~especially those with Xeon branding~~).

===============================================================================

** Pentium-M and Celerons usually lack SMT.

MPTable

-------------------------------------------------------------------------------

MP Floating Pointer Structure:

location: BIOS

physical address: 0x000fbd10

signature: '_MP_'

length: 16 bytes

version: 1.4

checksum: 0xc6

mode: Virtual Wire

-------------------------------------------------------------------------------

MP Config Table Header:

physical address: 0x000fbb10

signature: 'PCMP'

base table length: 508

version: 1.4

checksum: 0x84

OEM ID: 'QEMUCPU '

Product ID: '0.1 '

OEM table pointer: 0x00000000

OEM table size: 0

entry count: 34

local APIC address: 0xfee00000

extended table length: 0

extended table checksum: 0

-------------------------------------------------------------------------------

MP Config Base Table Entries:

--

Processors: APIC ID Version State Family Model Step Flags

0 0x11 BSP, usable 6 0 0 0x0201

1 0x11 AP, unusable 6 0 0 0x0201

2 0x11 AP, unusable 6 0 0 0x0201

3 0x11 AP, unusable 6 0 0 0x0201

4 0x11 AP, unusable 6 0 0 0x0201

5 0x11 AP, unusable 6 0 0 0x0201

6 0x11 AP, unusable 6 0 0 0x0201

7 0x11 AP, unusable 6 0 0 0x0201

8 0x11 AP, unusable 6 0 0 0x0201

9 0x11 AP, unusable 6 0 0 0x0201

10 0x11 AP, unusable 6 0 0 0x0201

11 0x11 AP, unusable 6 0 0 0x0201

12 0x11 AP, unusable 6 0 0 0x0201

13 0x11 AP, unusable 6 0 0 0x0201

14 0x11 AP, unusable 6 0 0 0x0201

15 0x11 AP, unusable 6 0 0 0x0201

--

Bus: Bus ID Type

0 ISA

--

I/O APICs: APIC ID Version State Address

1 0x11 usable 0xfec00000

--

I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#

INT conforms conforms 0 0 1 0

INT conforms conforms 0 1 1 1

INT conforms conforms 0 2 1 2

INT conforms conforms 0 3 1 3

INT conforms conforms 0 4 1 4

INT conforms conforms 0 5 1 5

INT conforms conforms 0 6 1 6

INT conforms conforms 0 7 1 7

INT conforms conforms 0 8 1 8

INT conforms conforms 0 9 1 9

INT conforms conforms 0 10 1 10

INT conforms conforms 0 11 1 11

INT conforms conforms 0 12 1 12

INT conforms conforms 0 13 1 13

INT conforms conforms 0 14 1 14

INT conforms conforms 0 15 1 15

===============================================================================

[bryhlath](0) $ </pre>

==/proc/cpuinfo==

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* [http://osdir.com/ml/linux.ports.x86-64.general/2005-10/msg00022.html This LKML thread] provides much information

* The [[cpuid]] instruction can interrogate each processing unit

* [[Cpuset|CPUsets]]

* "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network

[[Category: x86]]

[[CATEGORY: Hardware]]

SMP on x86: Difference between revisions

Dank (talk | contribs)

@@ Line 1: / Line 1: @@
 The primary specification for multiprocessor [[x86]]-based setups is the [http://www.intel.com/design/pentium/datashts/242016.HTM Intel MultiProcessor Specification] (last updated, AFAIK, to revision-006 on 1995-05-15).
+==SMT==
+* HyperThreading (Intel SMT) requires CPU, BIOS and OS support. Introduced on the P4.
+** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).
+** Pentium-M and Celerons usually lack SMT.
+* Unduplicated resources are either split or shared between logical cores:
+** Shared: reservation stations, data caches
+** Split: reorder buffers, load/store buffers
+** Duplicated: registers
+* No programmable priority control exported, no implicit priorities defined
+==Intel MP IDs==
+* Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID
+** The initial APIC ID can be retrieved via [[cpuid]], as can packaging data:
+*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured
+*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured
+*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel
+*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors
+*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore
+* APIC ID is formed of SMT_ID|CORE_ID|PACKAGE_ID, having widths defined by the packaging data:
+** SMT_ID is 0 bits on a non-HyperThreaded processor.
+** CORE_ID is 0 bits on a unicore package
+** All remaining bits are devoted to PACKAGE_ID
 ==Interrupts==
 * IO-APIC routes hardware interrupts to various CPUs ([http://www.mjmwired.net/kernel/Documentation/x86/i386/IO-APIC.txt Linux's IO-APIC.txt])
@@ Line 27: / Line 51: @@
 MIS:          0
 [recombinator](0) $ </pre>
-==[[ACPI]]==
+==Discovery==
-* The MADT table can supply multiprocessor configuration
+* [[ACPI]]'s MADT table can supply multiprocessor configuration, and is usually used if present
-* MP Table
+* MP Table. The FreeBSD program <tt>mptable(1)</tt> can dump this:
-* Interactions with [[cpuid]]
+<pre>[bryhlath](0) $ sudo mptable
-* HyperThreading (Intel SMT) requires CPU, BIOS and OS support. Introduced on the P4.
-** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding).
+===============================================================================
-** Pentium-M and Celerons usually lack SMT.
+MPTable
+-------------------------------------------------------------------------------
+MP Floating Pointer Structure:
+  location:			BIOS
+  physical address:		0x000fbd10
+  signature:			'_MP_'
+  length:			16 bytes
+  version:			1.4
+  checksum:			0xc6
+  mode:				Virtual Wire
+-------------------------------------------------------------------------------
+MP Config Table Header:
+  physical address:		0x000fbb10
+  signature:			'PCMP'
+  base table length:		508
+  version:			1.4
+  checksum:			0x84
+  OEM ID:			'QEMUCPU '
+  Product ID:			'0.1         '
+  OEM table pointer:		0x00000000
+  OEM table size:		0
+  entry count:			34
+  local APIC address:		0xfee00000
+  extended table length:	0
+  extended table checksum:	0
+-------------------------------------------------------------------------------
+MP Config Base Table Entries:
+--
+Processors:	APIC ID	Version	State		Family	Model	Step	Flags
+	 0x11	 BSP, usable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+	 0x11	 AP, unusable	 6	 0	 0	 0x0201
+--
+Bus:		Bus ID	Type
+	 ISA
+--
+I/O APICs:	APIC ID	Version	State		Address
+	 0x11	 usable		 0xfec00000
+--
+I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
+		INT	 conforms    conforms	     0	   0	      1	   0
+		INT	 conforms    conforms	     0	   1	      1	   1
+		INT	 conforms    conforms	     0	   2	      1	   2
+		INT	 conforms    conforms	     0	   3	      1	   3
+		INT	 conforms    conforms	     0	   4	      1	   4
+		INT	 conforms    conforms	     0	   5	      1	   5
+		INT	 conforms    conforms	     0	   6	      1	   6
+		INT	 conforms    conforms	     0	   7	      1	   7
+		INT	 conforms    conforms	     0	   8	      1	   8
+		INT	 conforms    conforms	     0	   9	      1	   9
+		INT	 conforms    conforms	     0	  10	      1	  10
+		INT	 conforms    conforms	     0	  11	      1	  11
+		INT	 conforms    conforms	     0	  12	      1	  12
+		INT	 conforms    conforms	     0	  13	      1	  13
+		INT	 conforms    conforms	     0	  14	      1	  14
+		INT	 conforms    conforms	     0	  15	      1	  15
+===============================================================================
+[bryhlath](0) $ </pre>
 ==/proc/cpuinfo==
@@ Line 389: / Line 495: @@
 * [http://osdir.com/ml/linux.ports.x86-64.general/2005-10/msg00022.html This LKML thread] provides much information
 * The [[cpuid]] instruction can interrogate each processing unit
+* [[Cpuset|CPUsets]]
+* "[http://software.intel.com/en-us/articles/multi-core-detect/ Detecting Multicore Processors]", Intel Software Network
 [[Category: x86]]
+[[CATEGORY: Hardware]]