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SMBus: Difference between revisions
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(Created page with "SMBus, designed by Intel and Duracell, is very similar to I<sup>2</sup>C from Philips. It is a single-ended two-wire protocol. It supports V<sub>DD</sub> from 3V to 5V (SMBus 2.0) or 1.8V to 5V (SMBus 3.0). ==Differences from I<sup>2</sup>C== * Clock low timeout at 35ms, and a minimum clock frequency of 10 kHz to support this. * Shared alert/interrupt signal") |
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SMBus, designed by Intel and Duracell, is very similar to I<sup>2</sup>C from Philips. It is a single-ended two-wire protocol. It supports V<sub>DD</sub> from 3V to 5V (SMBus 2.0) or 1.8V to 5V (SMBus 3.0). | SMBus, designed by Intel and Duracell, is very similar to I<sup>2</sup>C from Philips. It is a single-ended two-wire protocol. It supports V<sub>DD</sub> from 3V to 5V (SMBus 2.0) or 1.8V to 5V (SMBus 3.0). | ||
==Standards== | |||
* [https://smbus.org/specs/SMBus_3_3_1_20241020.pdf SMBus 3.1.1], 2024-10-20 | |||
* [https://smbus.org/specs/SMBus_3_0_20141220.pdf SMBus 3.0], 2014-12-20 | |||
* [https://smbus.org/specs/smbus20.pdf SMBus 2.0], 2000-08-03 | |||
* [https://www.smbus.org/specs/smb10.pdf SMBus 1.0], 1995-12-15 | |||
==Differences from I<sup>2</sup>C== | ==Differences from I<sup>2</sup>C== | ||
* Clock low timeout at 35ms, and a minimum clock frequency of 10 kHz to support this. | * Clock low timeout at 35ms, and a minimum clock frequency of 10 kHz to support this. | ||
* Shared alert/interrupt signal | * Shared alert/interrupt signal | ||
Latest revision as of 05:53, 14 January 2025
SMBus, designed by Intel and Duracell, is very similar to I2C from Philips. It is a single-ended two-wire protocol. It supports VDD from 3V to 5V (SMBus 2.0) or 1.8V to 5V (SMBus 3.0).
Standards
- SMBus 3.1.1, 2024-10-20
- SMBus 3.0, 2014-12-20
- SMBus 2.0, 2000-08-03
- SMBus 1.0, 1995-12-15
Differences from I2C
- Clock low timeout at 35ms, and a minimum clock frequency of 10 kHz to support this.
- Shared alert/interrupt signal
