SMP on x86: Difference between revisions
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==Intel MP IDs== | ==Intel MP IDs== | ||
* Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID | * Each logical processor is assigned a unique (but not necessarily sequential) 8-bit identifier at boot, the APIC ID | ||
** The initial APIC ID can be retrieved via [[cpuid]], as can | ** The initial APIC ID can be retrieved via [[cpuid]], as can packaging data: | ||
*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured | *** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured | ||
*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured | *** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured | ||
*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel | *** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel | ||
*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors | *** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors | ||
*** These last two require leaf level 4 [[cpuid]] support; if it is not provided, the package is a unicore | |||
* APIC ID is formed of SMT_ID|CORE_ID|PACKAGE_ID, having widths defined by the packaging data | |||
** SMT_ID is 0 bits on a non-HyperThreaded processor. | |||
** CORE_ID is 0 bits on a unicore package | |||
** All remaining bits are devoted to PACKAGE_ID | |||
==Interrupts== | ==Interrupts== | ||