Architecture: Difference between revisions

In the sequential execution model, each processing unit contains a program counter. The processor fetches the first instruction from memory, as indexed by the program counter. The program counter is then incremented. The instruction's operands, if any, are fetched, and it is executed. Execution might result in changes to the architectural state (including the program counter) of the processor, to memory, and/or to I/O devices. These changes are committed, and the next instruction is fetched. Each instruction might correspond to many clock cycles. This model is dominant among general-purpose microprocessors; for other models, see [http://en.wikipedia.org/wiki/Dataflow_architecture dataflow architectures] and [http://en.wikipedia.org/wiki/Transport_triggered_architecture transport-triggered architectures]. Out-of-order processors combine stored, serialized programs with data flow-based triggering, yielding "restricted data flow architectures".

==Parallelism==