Libtorque

My project for Professor Rich Vuduc's Fall 2009 CSE6230, libtorque is a multithreaded event library for UNIX designed to take full advantage of the manycore, heterogenous, NUMA future. Previous, non-threaded event libraries include libevent, libev and liboop. My project proposal suggests motivation for libtorque: I believe it necessary to take scheduling and memory-placement decisions into account to most optimally handle events, especially on manycore machines and especially to handle unexpected traffic sets (denial of service attacks, oversubscribed pipes, mixed-latency connections, etc).

Resources

• git hosting from GitHub:
  • Available from the dankamongmen/libtorque project page
  • git clone from git://github.com/dankamongmen/libtorque.git
• bugzilla, hosted here on http://dank.qemfd.net/bugzilla/

Milestones

• 2009-11-19: CSE 6230 checkpoint
• 2009-12-10: CSE 6230 due date

Design/Functionality

libtorque exposes an affinity-managing, continuations-based, architecture-aware, multithreaded scheduler and various utility functions, including an architecture-, OS-, and thread-aware allocator with strong scheduler feedbacks. It can analyze arbitrary object code via libdl and libelf, discover where instructions live, and allocate around those areas. It can take dynamically balanced or (static) asymmetric interrupt loads into account. By making service decisions and allocations based on whole-system effects, libtorque provides low latency and high throughput under even pedantically asymmetric, irregular loads.

System discovery

• Full support for CPUID as most recently defined by Intel and AMD (more advanced, as of 2009-10-31, than x86info)
• Full support for Linux and FreeBSD's native cpuset libraries, and SGI's libcpuset and [libNUMA]
• Discovers and makes available, for each processor type:
  • ISA, ISA-specific capabilities, and number of concurrent threads supported (degrees of SMT)
  • Line count, associativity, line length, geometry, and type of all caches
  • Entry count, associativity, page size and type of all TLBs
  • Inclusiveness relationships among cache and TLB levels
  • APIC ID's and how caches are shared among them
  • More: properties of hardware prefetching, ability to support non-temporal loads (MOVNTDQA, PREFETCHNTA, etc)
• Discovers and makes available, for each memory node type:
  • Connected processor groups and relative distance information
  • Number of pages and bank geometry
  • More: OS page prefetching policy, error-recovery info

References/Prior Art

• Philip Mucci's "Linux Multicore Performance Analysis and Optimization in a Nutshell", delivered at NOTUR 2009
• Elmeleegy et al's "Lazy Asynchronous I/O", USENIX 2004
• PGAS: Kathy Yelick's "Performance and Productivity Opportunities using Global Address Space Programming Models", 2006
• Emery Berger's Hoard and other manycore-capable allocators (libumem aka magazined slab, Google's ctmalloc, etc).

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