Libtorque: Difference between revisions
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* Eker. "[http://www.ece.ncsu.edu/news/theses/etd-03302007-161856 Characterization of Context Switch Effects on L2 Cache]", 2007. | * Eker. "[http://www.ece.ncsu.edu/news/theses/etd-03302007-161856 Characterization of Context Switch Effects on L2 Cache]", 2007. | ||
* Williams, Vuduc, Oliker, Shalf, Yelick, Demmel. "[http://bebop.cs.berkeley.edu/pubs/williams2007-multicore-spmv-slides.pdf Tuning Sparse Matrix Vector Multiplication for multi-core SMPs]", 2007. | * Williams, Vuduc, Oliker, Shalf, Yelick, Demmel. "[http://bebop.cs.berkeley.edu/pubs/williams2007-multicore-spmv-slides.pdf Tuning Sparse Matrix Vector Multiplication for multi-core SMPs]", 2007. | ||
* Tsafrir | * Tsafrir. "[http://www.citeulike.org/user/dankamongmen/article/2052076 The context-switch overhead inflicted by hardware interrupts (and the enigma of do-nothing loops)]", 2007. | ||
* | * Yelick. "[http://www.sdsc.edu/pmac/workshops/geo2006/pubs/Yelick.pdf Performance and Productivity Opportunities using Global Address Space Programming Models]", 2006. | ||
* Mohamood. "[http://smartech.gatech.edu/handle/1853/10560 DLL-Conscious Instruction Fetch Optimization for SMT Processors]", 2006. | * Mohamood. "[http://smartech.gatech.edu/handle/1853/10560 DLL-Conscious Instruction Fetch Optimization for SMT Processors]", 2006. | ||
* Elmeleegy et al's "[http://www.cs.rice.edu/~kdiaa/laio/ Lazy Asynchronous I/O]", USENIX 2004. | * Elmeleegy et al's "[http://www.cs.rice.edu/~kdiaa/laio/ Lazy Asynchronous I/O]", USENIX 2004. | ||