CUDA: Difference between revisions
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* Pinned memory can be mapped directly into CUDAspace on ''integrated'' devices or in the presence of some IOMMUs. | * Pinned memory can be mapped directly into CUDAspace on ''integrated'' devices or in the presence of some IOMMUs. | ||
** "Zero (explicit)-copy" interface (can never hide all bus delays) | ** "Zero (explicit)-copy" interface (can never hide all bus delays) | ||
* Write-combining memory (configured via [[MTRR|MTRRs]] or [[ | * Write-combining memory (configured via [[MTRR|MTRRs]] or [[Page Attribute Tables|PATs]]) avoids PCI snoop requirements and maximizes linear throughput | ||
** Subtle side-effects; not to be used glibly or carelessly! | ** Subtle side-effects; not to be used glibly or carelessly! | ||