CUDA: Difference between revisions
| Line 122: | Line 122: | ||
===Streaming Multiprocessor=== | ===Streaming Multiprocessor=== | ||
* Each SM has a register file, fast local (''shared'') memory, a cache for | * Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of Stream Processors (SPs). | ||
** 8192 registers for compute capability <= 1.1, otherwise | ** 8192 registers for compute capability <= 1.1, otherwise | ||
** 16384 for compute capability <= 1.3 | ** 16384 for compute capability <= 1.3 | ||