CUDA: Difference between revisions
| Line 123: | Line 123: | ||
===Streaming Multiprocessor=== | ===Streaming Multiprocessor=== | ||
* Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of Stream Processors (SPs). | * Each SM has a register file, fast local (''shared'') memory, a cache for constant memory, an instruction cache (ROP), a multithreaded instruction dispatcher, and some number of [[#Stream Processor|Stream Processors]] (SPs). | ||
** 8192 registers for compute capability <= 1.1, otherwise | ** 8192 registers for compute capability <= 1.1, otherwise | ||
** 16384 for compute capability <= 1.3 | ** 16384 for compute capability <= 1.3 | ||
| Line 136: | Line 136: | ||
* Each time the kernel is instantiated, new grid and block dimensions may be provided. | * Each time the kernel is instantiated, new grid and block dimensions may be provided. | ||
* A block's threads, starting from threadId 0, are broken up into contiguous '''warps''' having some '''warp size''' number of threads. | * A block's threads, starting from threadId 0, are broken up into contiguous '''warps''' having some '''warp size''' number of threads. | ||
* Distributes work at ''thread'' granularity to [[#Stream Processor|SPs]]. | |||
===Stream Processor=== | |||
* In-order, multithreaded processor: latencies can be hidden only by TLP, not ILP. | |||
** Arithmetic intensity and parallelism are paramount! | |||
** Memory-bound kernels require sufficiently high ''occupancy'' (the ratio of concurrently-running warps to maximum possible concurrent warps (as applied, usually, to [[#Streaming Multiprocessor|SMs]])) to hide latency. | |||
{| border="1" | {| border="1" | ||
! Memory type | ! Memory type | ||