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Wallace tree: Difference between revisions
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A circuit which reduces the problem of summing n n-bit numbers to the problem of summing two O(n)-bit numbers, using floor(n/3) parallel carry-save adders. This reduces an n-way sum to a ceil(2n/3)-way sum, which can be recursively defined as another reducing Wallace tree. Usually defined as part of the Wallace tree multiplier. | A circuit which reduces the problem of summing n n-bit numbers to the problem of summing two O(n)-bit numbers, using floor(n/3) parallel carry-save adders. This reduces an n-way sum to a ceil(2n/3)-way sum, which can be recursively defined as another reducing Wallace tree. Usually defined as part of the [[Wallace Multiplier|Wallace tree multiplier]]. | ||
[[CATEGORY: Computer Science Eponyms]] | [[CATEGORY: Computer Science Eponyms]] | ||
Latest revision as of 02:25, 27 September 2012
A circuit which reduces the problem of summing n n-bit numbers to the problem of summing two O(n)-bit numbers, using floor(n/3) parallel carry-save adders. This reduces an n-way sum to a ceil(2n/3)-way sum, which can be recursively defined as another reducing Wallace tree. Usually defined as part of the Wallace tree multiplier.
