Winbond: Difference between revisions
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==[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GV]== | ==[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GV]== | ||
A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". The first 16 bytes of each Spare Area is used for ECC and bad block marking. | A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". The first 16 bytes of each Spare Area is used for ECC and bad block marking. | ||
Packagings include: | Packagings include: | ||
* 8-pad WSON 8x6mm (package code ZE) | * 8-pad WSON 8x6mm (package code ZE) | ||
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* 1x4 + 4x5 24-ball 8x6mm TFBGA (package code TB) | * 1x4 + 4x5 24-ball 8x6mm TFBGA (package code TB) | ||
* 4x6 24-ball 8x6mm TFBGA (package code TC) | * 4x6 24-ball 8x6mm TFBGA (package code TC) | ||
Lines: | Lines: | ||
* CLK serial clock input | * CLK serial clock input | ||