Winbond: Difference between revisions
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** MSB: Status register protect 0 | ** MSB: Status register protect 0 | ||
** B6, B5, B4, B3: Block protection bits, all initialized to 1 (unless set via OTP) | ** B6, B5, B4, B3: Block protection bits, all initialized to 1 (unless set via OTP) | ||
** B2: Type of protection | ** B2: TP (Type of protection). When 1, protection applies to the lower end of the protected blocks; when 0, the upper end | ||
*** When BP3 and either BP2 or BP1 are 1, TP is a don't care -- everything is protected | |||
*** When all BP bits are 0, TP is a don't care -- nothing is protected | |||
** B1: Write protection mode. Defaults to 0 (Software protection, Quad-SPI) | ** B1: Write protection mode. Defaults to 0 (Software protection, Quad-SPI) | ||
*** Hardware write protection (/WP, /HOLD) cannot be used with Quad-SPI | *** Hardware write protection (/WP, /HOLD) cannot be used with Quad-SPI | ||