SMP on x86: Difference between revisions
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** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding). | ** Found on (all) i7's, [http://www.intel.com/technology/atom/microarchitecture.htm some Atoms], and some P4's and Core2Duo's (especially those with Xeon branding). | ||
** Pentium-M and Celerons usually lack SMT. | ** Pentium-M and Celerons usually lack SMT. | ||
==Intel MP IDs== | |||
* Each logical processor is assigned a unique (but not necessarily sequential) identifier at boot, the APIC ID | |||
** The initial APIC ID can be retrieved via [[cpuid]], as can... | |||
*** "logical cores per package" (CPUID.1.EBX[23:16]): Maximum number of logical processors in a physical package, as manufactured | |||
*** "cores per package" (CPUID.4.EAX[31:26] + 1): Maximum number of physical processors (cores) in a physical package, as manufactured | |||
*** "logical processors sharing a cache" (CPUID.4.EAX[25:14] + 1): Maximum number of logical processors in a physical package sharing a given cachelevel | |||
*** Intel MP only addresses homogeneous setups, so these three values are (as of October 2009) equivalent for all processors | |||
==Interrupts== | ==Interrupts== | ||