Pages: Difference between revisions
No edit summary |
|||
| Line 1: | Line 1: | ||
==Hardware== | ==Hardware== | ||
[[File:X86 64.png|x86_64 page table layout|right]] | [[File:X86 64.png|x86_64 page table layout|right]] | ||
* PAE, page tables, PTEs, TLB, MMU -- explain ''FIXME'' | * PAE, PSE, PSE36, page tables, PTEs, TLB, MMU -- explain ''FIXME'' | ||
===UltraSPARC=== | ===UltraSPARC=== | ||
* UltraSPARC I and II - four page sizes. one instruction TLB, one data TLB, each 64 fully-associative entries, each capable of using any of the four page sizes. | * UltraSPARC I and II - four page sizes. one instruction TLB, one data TLB, each 64 fully-associative entries, each capable of using any of the four page sizes. | ||
| Line 9: | Line 9: | ||
* 4k default pages / 4M available | * 4k default pages / 4M available | ||
* 2M in PAE | * 2M in PAE | ||
* 1G on AMD processors implementing [[CPUID]] function 0x8000_0019 (see AMD Document 25481, "CPUID Specification", Revision 2.28) | |||
** Relevant descriptors are in EAX and EBX | |||
* Robert Collins's "[http://www.rcollins.org/articles/4mpages/4MOverview.html Understanding Page Size Extensions on the Pentium Processor]" and "[http://www.rcollins.org/articles/2mpages/2MPages.html Paging Extensions for the Pentium Pro Processor]" on x86.org | * Robert Collins's "[http://www.rcollins.org/articles/4mpages/4MOverview.html Understanding Page Size Extensions on the Pentium Processor]" and "[http://www.rcollins.org/articles/2mpages/2MPages.html Paging Extensions for the Pentium Pro Processor]" on x86.org | ||
===ia64=== | ===ia64=== | ||