Pages: Difference between revisions
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==Hardware== | ==Hardware== | ||
[[File:X86 64.png|x86_64 page table layout|right]] | [[File:X86 64.png|x86_64 page table layout|right]] | ||
* PAE, PSE, PSE36, page tables, PTEs, TLB, MMU -- explain ''FIXME'' | * PAE, PSE, PSE36, page tables, PTEs, TLB, MMU, PGD -- explain ''FIXME'' | ||
===UltraSPARC=== | ===UltraSPARC=== | ||
* UltraSPARC I and II - four page sizes. one instruction TLB, one data TLB, each 64 fully-associative entries, each capable of using any of the four page sizes. | * UltraSPARC I and II - four page sizes. one instruction TLB, one data TLB, each 64 fully-associative entries, each capable of using any of the four page sizes. | ||