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* Forwarding results between integer, integer SIMD, and FP units adds latency compared to forwards within the domain.
* Forwarding results between integer, integer SIMD, and FP units adds latency compared to forwards within the domain.
* One register may be written per cycle.
* One register may be written per cycle.
* Move to [[QPI (Quick Path Interconnect)]]
* 48 load buffers, 32 store buffers, 10 fill buffers.
* 48 load buffers, 32 store buffers, 10 fill buffers.
* 36 reservation stations (up from 32), 128 ROB entries (up from 96).
* 36 reservation stations (up from 32), 128 ROB entries (up from 96).
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