Nehalem

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[[File:IAmNehalem.jpg|thumb|right|Ehyeh asher ehyeh]]

[[File:Intel Nehalem arch.png|thumb|right|Nehalem microarchitecture]]

* Move to 133MHz [[QPI (Quick Path Interconnect)]], against which the CPU clock is multiplied

* Reintroduction of [[SMP on x86#SMT|SMT (HyperThreading)]]

* Store-forwarding aliasing issue on 4k strides.

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* Forwarding results between integer, integer SIMD, and FP units adds latency compared to forwards within the domain.

* One register may be written per cycle.

* Move to [[QPI (Quick Path Interconnect)]]

* 48 load buffers (up from 32), 32 store buffers (up from 20), 10 fill buffers.

* 48 load buffers, 32 store buffers, 10 fill buffers.

* 36 reservation stations (up from 32), 128 ROB entries (up from 96).

* Calltrace cache of 16 entries.

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* Be sure to use register parameter-passing conventions, not the stack, to avoid stalls on store-forward of high-latency floating point stores.

* Peak issue rate of 1 128-bit load and 1 128-bit store per cycle.

==See Also==

* The Dark Knight's [http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448 AnandTech] article, 2008-11-03.

[[Category: x86]]

Nehalem: Difference between revisions

@@ Line 1: / Line 1: @@
 [[File:IAmNehalem.jpg|thumb|right|Ehyeh asher ehyeh]]
 [[File:Intel Nehalem arch.png|thumb|right|Nehalem microarchitecture]]
+* Move to 133MHz [[QPI (Quick Path Interconnect)]], against which the CPU clock is multiplied
 * Reintroduction of [[SMP on x86#SMT|SMT (HyperThreading)]]
 * Store-forwarding aliasing issue on 4k strides.
@@ Line 9: / Line 10: @@
 * Forwarding results between integer, integer SIMD, and FP units adds latency compared to forwards within the domain.
 * One register may be written per cycle.
-* Move to [[QPI (Quick Path Interconnect)]]
+* 48 load buffers (up from 32), 32 store buffers (up from 20), 10 fill buffers.
-* 48 load buffers, 32 store buffers, 10 fill buffers.
 * 36 reservation stations (up from 32), 128 ROB entries (up from 96).
 * Calltrace cache of 16 entries.
@@ Line 21: / Line 21: @@
 * Be sure to use register parameter-passing conventions, not the stack, to avoid stalls on store-forward of high-latency floating point stores.
 * Peak issue rate of 1 128-bit load and 1 128-bit store per cycle.
+==See Also==
+* The Dark Knight's [http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3448 AnandTech] article, 2008-11-03.
 [[Category: x86]]