Check out my first novel, midnight's simulacra!
MTRR: Difference between revisions
From dankwiki
(Created page with 'Until the P6, MTRRs governed only peripherals. Following the P6, they also applied to memory accesses by the processor. CATEGORY: x86') |
No edit summary |
||
| Line 1: | Line 1: | ||
Until the P6, MTRRs governed only peripherals. Following the P6, they also applied to memory accesses by the processor. | Memory Type Range-Registers define write policies for ranges of memory on the x86 architecture. Until the P6, MTRRs governed only peripherals. Following the P6, they also applied to memory accesses by the processor. MTRR's have largely been superseded by [[Page Attribute Tables]]. | ||
==MTRR States== | |||
For more detail, see my entry on [[Architecture#Caches caches]]. | |||
* Uncacheable: Must never be cached. Primarily used for memory-mapped I/O. | |||
* Write-through: Write both to cache and backing memory. | |||
* Write-combining: Temporarily store to a write-combining buffer, and write in burst mode | |||
* Write-protect: Writes are not allowed | |||
* Write-back: Write to cache immediately, but to memory only when forced | |||
[[CATEGORY: x86]] | [[CATEGORY: x86]] | ||
Revision as of 00:14, 21 April 2010
Memory Type Range-Registers define write policies for ranges of memory on the x86 architecture. Until the P6, MTRRs governed only peripherals. Following the P6, they also applied to memory accesses by the processor. MTRR's have largely been superseded by Page Attribute Tables.
MTRR States
For more detail, see my entry on Architecture#Caches caches.
- Uncacheable: Must never be cached. Primarily used for memory-mapped I/O.
- Write-through: Write both to cache and backing memory.
- Write-combining: Temporarily store to a write-combining buffer, and write in burst mode
- Write-protect: Writes are not allowed
- Write-back: Write to cache immediately, but to memory only when forced
