Sandy Bridge: Difference between revisions
| Line 80: | Line 80: | ||
* Different clock and power plane | * Different clock and power plane | ||
* Provides an IOMMU | * Provides an IOMMU | ||
* 16 PCIe 2.0 lanes | * 16 PCIe 2.0 lanes (2x16b @ 5GT/s) | ||
* Dual-channel DDR3 | * Dual-channel DDR3 (2x8b @ FSB x KT/s) | ||
===IGP=== | ===IGP=== | ||