Check out my first novel, midnight's simulacra!

Winbond: Difference between revisions

From dankwiki
No edit summary
Line 1: Line 1:
[https://www.winbond.com/hq/ Winbond] of Taiwan manufactures semiconductor devices, including flash storage.
[https://www.winbond.com/hq/ Winbond] of Taiwan manufactures semiconductor devices, including flash storage.


==[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GV]==
==[https://www.winbond.com/resource-files/w25n01gv%20revg%20032116.pdf W25N01GVxxIG/IT]==
A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte.
A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte.


Packagings include:
The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.
 
===Packages===
* 8-pad WSON 8x6mm (package code ZE)
* 8-pad WSON 8x6mm (package code ZE)
* 16-pin SOIC 300-mil (package code SF)
* 16-pin SOIC 300-mil (package code SF)
Line 10: Line 12:
* 4x6 24-ball 8x6mm TFBGA (package code TC)
* 4x6 24-ball 8x6mm TFBGA (package code TC)


Lines:
===Lines===
* CLK serial clock input
* CLK serial clock input
* /CS chip select input
* /CS chip select input
Line 16: Line 18:
** Transition to low places device into active mode
** Transition to low places device into active mode
** /CS must track VCC during initialization and shutdown
** /CS must track VCC during initialization and shutdown
* DI (IO0) data input / data io0
* DI (IO0) data input / data io0
* DO (IO1) data output / data io1
* DO (IO1) data output / data io1
Line 24: Line 25:
* GND
* GND
/WP and /HOLD are only for SPI/Dual-SPI (Quad-SPI uses data io 0--3). Data is always written on the rising edge of CLK, and read on the falling edge. SPI must write through DO and read through DI. Dual- and Quad-SPI treat data io pins as bidirectional.
/WP and /HOLD are only for SPI/Dual-SPI (Quad-SPI uses data io 0--3). Data is always written on the rising edge of CLK, and read on the falling edge. SPI must write through DO and read through DI. Dual- and Quad-SPI treat data io pins as bidirectional.
===Registers===
Used with the ReadStatusRegister and WriteStatusRegister commands:
* Protection Register (SR1)
* Configuration Register (SR2)
** MSB: OTP lock. Once set to 1, the OTP area (10 2KB pages) cannot be reprogrammed.
** B6: OTP access enable. Must be set to 1 to access OTP area.
** B5: SR1 lock. Once set to 1, selected SR1 values are OTP-locked.
** B4: ECC enable. Defaults to 1. Controls on-device bidirectional ECC.
** B3: BUF mode select. Default depends on part number (IG defaults to 1). 1 is buffer read mode, 0 is continuous.
*** Buffer mode: provided a starting byte and a page, returns the page starting at that byte, plus the Spare Area
*** Continuous mode: provided a page, returns (multiple pages of) memory starting at the first byte of that page
*** Only buffer mode allows the Spare Area to be read
* Status Register (SR3)

Revision as of 04:28, 29 March 2019

Winbond of Taiwan manufactures semiconductor devices, including flash storage.

W25N01GVxxIG/IT

A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte.

The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.

Packages

  • 8-pad WSON 8x6mm (package code ZE)
  • 16-pin SOIC 300-mil (package code SF)
  • 1x4 + 4x5 24-ball 8x6mm TFBGA (package code TB)
  • 4x6 24-ball 8x6mm TFBGA (package code TC)

Lines

  • CLK serial clock input
  • /CS chip select input
    • High deselects the device, putting it into standby mode (reduced power consumption)
    • Transition to low places device into active mode
    • /CS must track VCC during initialization and shutdown
  • DI (IO0) data input / data io0
  • DO (IO1) data output / data io1
  • /WP (IO2) write protect input / data io2
  • /HOLD (IO3) hold input / data io3
  • VCC power (2.7V--3.6V)
  • GND

/WP and /HOLD are only for SPI/Dual-SPI (Quad-SPI uses data io 0--3). Data is always written on the rising edge of CLK, and read on the falling edge. SPI must write through DO and read through DI. Dual- and Quad-SPI treat data io pins as bidirectional.

Registers

Used with the ReadStatusRegister and WriteStatusRegister commands:

  • Protection Register (SR1)
  • Configuration Register (SR2)
    • MSB: OTP lock. Once set to 1, the OTP area (10 2KB pages) cannot be reprogrammed.
    • B6: OTP access enable. Must be set to 1 to access OTP area.
    • B5: SR1 lock. Once set to 1, selected SR1 values are OTP-locked.
    • B4: ECC enable. Defaults to 1. Controls on-device bidirectional ECC.
    • B3: BUF mode select. Default depends on part number (IG defaults to 1). 1 is buffer read mode, 0 is continuous.
      • Buffer mode: provided a starting byte and a page, returns the page starting at that byte, plus the Spare Area
      • Continuous mode: provided a page, returns (multiple pages of) memory starting at the first byte of that page
      • Only buffer mode allows the Spare Area to be read
  • Status Register (SR3)
Retrieved from "https://nick-black.com/dankwiki/index.php?title=Winbond&oldid=5940"