Winbond

Winbond of Taiwan manufactures semiconductor devices, including flash storage.

W25N01GVxxIG/IT

A 1Gb (128MB) Quad-SPI SLC NAND chip of 1K 128KB blocks (each made up of 64 ECC-protected 2KB pages), capable of up to 104MHz Quad-SPI. Each page, in addition to the 2048 usable bytes, contains a 64-byte "Spare Area". Writes load 2,112 bytes. When on-device ECC is enabled, the majority of the Spare Area is used for ECC and bad block marking, though 2 unprotected and 4 ECC-protected bits are available to the user in each of 4 16-byte lines. When on-device ECC is disabled, the 64 bytes of the Spare Area are available to the user. The serial NAND employs 32-bit addresses: the four MSB are unused, 10 bits select the block, 6 bits select the page, and the 12 LSB specify the byte.

The xx refers to the package code. The IT part sets the BUF mode selector to 0 on initialization. The IG part sets BUF to 1. Both allow the mode to be configured by writing to the BUF bit of the Configuration Register.

Packages

• 8-pad WSON 8x6mm (package code ZE)
• 16-pin SOIC 300-mil (package code SF)
• 1x4 + 4x5 24-ball 8x6mm TFBGA (package code TB)
• 4x6 24-ball 8x6mm TFBGA (package code TC)

Lines

• CLK serial clock input
• /CS chip select input
  • High deselects the device, putting it into standby mode (reduced power consumption)
  • Transition to low places device into active mode
  • /CS must track VCC during initialization and shutdown
• DI (IO0) data input / I/O-0
  • SPI must use this for writing. Dual- and Quad-SPI use it bidirectionally.
• DO (IO1) data output / I/O-1
  • SPI must use this for reading. Dual- and Quad-SPI use it bidirectionally.
• /WP (IO2) write protect input / I/O-2
  • Used only in Hardware Protection mode (incompatible with Quad-SPI)
• /HOLD (IO3) hold input / I/O-3
  • Used only in Hardware Protection mode (incompatible with Quad-SPI)
• VCC power (2.7V--3.6V)
• GND

Data is written on the rising edge of CLK, and read on the falling edge.

Registers

Used with the ReadStatusRegister and WriteStatusRegister commands:

• Protection Register (SR1)
  • MSB: Status register protect 0
  • B6, B5, B4, B3: Block protection bits, all initialized to 1 (unless set via OTP)
  • B2: TP (Type of protection). When 1, protection applies to the lower end of the protected blocks; when 0, the upper end
    • When BP3 and either BP2 or BP1 are 1, TP is a don't care -- everything is protected
    • When all BP bits are 0, TP is a don't care -- nothing is protected
  • B1: Write protection mode. Defaults to 0 (Software protection, Quad-SPI)
    • Hardware write protection (/WP, /HOLD) cannot be used with Quad-SPI
  • LSB: Status register protect 1
• Configuration Register (SR2)
  • MSB: OTP lock. Once set to 1, the OTP area (10 2KB pages) cannot be reprogrammed.
  • B6: OTP access enable. Must be set to 1 to access OTP area.
  • B5: SR1 lock. Once set to 1, selected SR1 values are OTP-locked.
  • B4: ECC enable. Defaults to 1. Controls on-device bidirectional ECC.
  • B3: BUF mode select. Default depends on part number (IG defaults to 1). 1 is buffer read mode, 0 is continuous.
    • Buffer mode: provided a starting byte and a page, returns the page starting at that byte, plus the Spare Area
    • Continuous mode: provided a page, returns (multiple pages of) memory starting at the first byte of that page
    • Only buffer mode allows the Spare Area to be read
  • B2, B1, LSB: reserved
• Status Register (SR3)
  • MSB: reserved
  • B6: LUT full, set to 1 when all 20 entries of the LUT are used
  • B5: ECC-1 (ECC status), set to 0 on successful read (even with corrections), 1 on uncorrected error
  • B4: ECC-0 (ECC details)
    • If ECC-1 is 0, 0 indicates no corrections, 1 indicates corrections.
    • If ECC-1 is 1, 0 indicates unusable page, 1 indicates multiple unusable pages (during continuous read)
    • Both ECC bits are reset to 0 only on initialization and following RESET
  • B3: PFAIL (Program failure), set to 1 when a ProgramExecute command fails
  • B2: EFAIL (Erase failure), set to 1 when a BlockErase command fails
    • Both PFAIL and EFAIL are reset at the beginning of each ProgramExecute or BlockErase
  • B1: Write-enabled latch, set to 1 following WriteEnable instruction, set to 0 following many instructions
  • B0: Busy, set to 1 while instructions are not being accepted following many instructions

Instructions

27 instructions are supported. Instruction read is initiated on the falling edge of /CS, and completed on the rising edge (8 clocks later). Write, Program, and Erase instructions must complete on a byte boundary (rising /CS), and most instructions are ignored when the BUSY bit of SR3 is set.