Check out my first novel, midnight's simulacra!
Direct Cache Access: Difference between revisions
From dankwiki
No edit summary |
No edit summary |
||
| Line 1: | Line 1: | ||
From [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction", section 3.1.10: When EAX is initialized to a value of 9, the [[CPUID]] instruction returns DCA information in the EAX, EBX, ECX and EDX registers. | From [http://www.intel.com/Assets/PDF/appnote/241618.pdf Intel Application Note 485], "Intel Processor Identification and the CPUID Instruction", section 3.1.10: When EAX is initialized to a value of 9, the [[cpuid|CPUID]] instruction returns DCA information in the EAX, EBX, ECX and EDX registers. | ||
* EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h) | * EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h) | ||
* EBX: Reserved | * EBX: Reserved | ||
Revision as of 12:00, 27 June 2009
From Intel Application Note 485, "Intel Processor Identification and the CPUID Instruction", section 3.1.10: When EAX is initialized to a value of 9, the CPUID instruction returns DCA information in the EAX, EBX, ECX and EDX registers.
- EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)
- EBX: Reserved
- ECX: Reserved
- EDX: Reserved
