Check out my first novel, midnight's simulacra!
Direct Cache Access: Difference between revisions
From dankwiki
No edit summary |
No edit summary |
||
| Line 11: | Line 11: | ||
*[http://doi.ieeecomputersociety.org/10.1109/MC.2004.223 "TCP Onloading for Data Center Severs"] | *[http://doi.ieeecomputersociety.org/10.1109/MC.2004.223 "TCP Onloading for Data Center Severs"] | ||
*[http://www.eecs.umich.edu/techreports/cse/2004/CSE-TR-505-04.pdf "Analyzing NIC Overheads in Network-Intensive Workloads"] | *[http://www.eecs.umich.edu/techreports/cse/2004/CSE-TR-505-04.pdf "Analyzing NIC Overheads in Network-Intensive Workloads"] | ||
[[Category: Hardware]] | |||
[[Category: x86]] | |||
Revision as of 00:53, 22 January 2023
From Intel Application Note 485, "Intel Processor Identification and the CPUID Instruction", section 3.1.10:
When EAX is initialized to a value of 9, the CPUID instruction returns DCA information in the EAX, EBX, ECX and EDX registers:
- EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)
- EBX: Reserved
- ECX: Reserved
- EDX: Reserved
I've got a list of DCA-enabled NICs.
