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Direct Cache Access: Difference between revisions

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*EDX: Reserved</blockquote>
*EDX: Reserved</blockquote>
I've got a list of [[Hardware detritus#NICs|DCA-enabled NICs]].
I've got a list of [[Hardware detritus#NICs|DCA-enabled NICs]].


==See Also==
==See Also==
[http://www.stanford.edu/group/comparch/papers/huggahalli05.pdf "Direct Cache Access for High Bandwidth Network I/O"]
*[http://www.stanford.edu/group/comparch/papers/huggahalli05.pdf "Direct Cache Access for High Bandwidth Network I/O"]
[http://doi.ieeecomputersociety.org/10.1109/MC.2004.223 "TCP Onloading for Data Center Severs"]
*[http://doi.ieeecomputersociety.org/10.1109/MC.2004.223 "TCP Onloading for Data Center Severs"]
*[http://www.eecs.umich.edu/techreports/cse/2004/CSE-TR-505-04.pdf "Analyzing NIC Overheads in Network-Intensive Workloads"]

Revision as of 12:19, 27 June 2009

From Intel Application Note 485, "Intel Processor Identification and the CPUID Instruction", section 3.1.10:

When EAX is initialized to a value of 9, the CPUID instruction returns DCA information in the EAX, EBX, ECX and EDX registers:

  • EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)
  • EBX: Reserved
  • ECX: Reserved
  • EDX: Reserved

I've got a list of DCA-enabled NICs.

See Also