Direct Cache Access

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From Intel Application Note 485, "Intel Processor Identification and the CPUID Instruction", section 3.1.10:

When EAX is initialized to a value of 9, the CPUID instruction returns DCA information in the EAX, EBX, ECX and EDX registers:

  • EAX: Value of PLATFORM_DCA_CAP MSR Bits [31:0] (Offset 1F8h)
  • EBX: Reserved
  • ECX: Reserved
  • EDX: Reserved

I've got a list of DCA-enabled NICs.

See Also

"Direct Cache Access for High Bandwidth Network I/O" "TCP Onloading for Data Center Severs"