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File:Memoryhierarchy.png
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Diagram (from Patterson & Hennessy's Computer Architecture: A Quantitative Approach) of a hypothetical memory hierarchy's path from virtual address access to L2 cache access. 8K pages, direct-mapped 256-entry TLB, direct-mapped 8K L1 (64 byte lines), direct-mapped 4M L2 (64 byte blocks), 64-bit virtual address, 40 bit physical address.
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current | 14:15, 21 September 2009 | 904 × 887 (94 KB) | Dank (talk | contribs) | Diagram (from Patterson & Hennessy's ''Computer Architecture: A Quantitative Approach'') of a hypothetical memory hierarchy's path from virtual address access to L2 cache access. 8K pages, direct-mapped 256-entry TLB, direct-mapped 8K L1 (64 byte lines), |
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